Run pre-commit

build/bnn-pynq/specialize_layers_config.json

@@ -57,4 +57,4 @@
   "LabelSelect_0": {
     "preferred_impl_style": "hls"
   }
-}
+}

build/gtsrb/models/download-model.sh

@@ -1,2 +1,2 @@
 #!/bin/bash
-wget https://github.com/fastmachinelearning/qonnx_model_zoo/raw/feature/gtsrb_cnv/models/GTSRB/Brevitas_CNV1W1A/cnv_1w1a_gtsrb.onnx
+wget https://github.com/fastmachinelearning/qonnx_model_zoo/raw/feature/gtsrb_cnv/models/GTSRB/Brevitas_CNV1W1A/cnv_1w1a_gtsrb.onnx

build/resnet50/custom_steps.py

@@ -1,4 +1,5 @@
-# Copyright (c) 2020, Xilinx
+# Copyright (C) 2020-2022, Xilinx, Inc.
+# Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -95,23 +96,8 @@
     ShellFlowType,
 )
 
-from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
-from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
-from finn.transformation.fpgadataflow.replace_verilog_relpaths import (
-    ReplaceVerilogRelPaths,
-)
-
 from finn.transformation.move_reshape import RemoveCNVtoFCFlatten
 
-from qonnx.util.config import extract_model_config_to_json
-from finn.transformation.fpgadataflow.set_fifo_depths import (
-    InsertAndSetFIFODepths,
-    RemoveShallowFIFOs,
-    SplitLargeFIFOs,
-)
-from finn.transformation.fpgadataflow.insert_dwc import InsertDWC
-from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
-
 
 def step_resnet50_tidy(model: ModelWrapper, cfg: DataflowBuildConfig):
     model = model.transform(GiveUniqueParameterTensors())
@@ -222,6 +208,7 @@ def step_resnet50_convert_to_hw(model: ModelWrapper, cfg: DataflowBuildConfig):
 
     return model
 
+
 def step_resnet50_slr_floorplan(model: ModelWrapper, cfg: DataflowBuildConfig):
     if cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
         try:

build/resnet50/specialize_layers_config.json

@@ -525,4 +525,4 @@
   "LabelSelect_0": {
     "preferred_impl_style": "hls"
   }
-}
+}

build/vgg10-radioml/build.py

@@ -110,7 +110,7 @@ def select_build_steps(platform):
         shell_flow_type=shell_flow_type,
         vitis_platform=vitis_platform,
         folding_config_file="folding_config/%s_folding_config.json" % platform_name,
-        split_large_fifos = True,
+        split_large_fifos=True,
         standalone_thresholds=True,
         # enable extra performance optimizations (physopt)
         vitis_opt_strategy=build_cfg.VitisOptStrategyCfg.PERFORMANCE_BEST,

build/vgg10-radioml/folding_config/ZCU104_folding_config.json

@@ -218,4 +218,4 @@
   "LabelSelect_hls_0": {
     "PE": 1
   }
-}
+}

build/vgg10-radioml/specialize_layers_config.json

@@ -126,4 +126,4 @@
   "LabelSelect_0": {
     "preferred_impl_style": "hls"
   }
-}
+}

finn_examples/models.py

@@ -363,6 +363,7 @@ def resnet50_w1a2_imagenet(target_platform=None):
         runtime_weight_dir=runtime_weight_dir,
     )
 
+
 def vgg10_w4a4_radioml(target_platform=None):
     target_platform = resolve_target_platform(target_platform)
     driver_mode = get_driver_mode()
@@ -376,6 +377,7 @@ def vgg10_w4a4_radioml(target_platform=None):
         fclk_mhz=fclk_mhz,
     )
 
+
 def mlp_w2a2_unsw_nb15(target_platform=None):
     target_platform = resolve_target_platform(target_platform)
     driver_mode = get_driver_mode()
@@ -386,9 +388,10 @@ def mlp_w2a2_unsw_nb15(target_platform=None):
         filename, driver_mode, _unsw_nb15_mlp_io_shape_dict, fclk_mhz=fclk_mhz
     )
 
+
 def cnv_w1a1_gtsrb(target_platform=None):
     target_platform = resolve_target_platform(target_platform)
     driver_mode = get_driver_mode()
     model_name = "cnv-gtsrb-w1a1"
     filename = find_bitfile(model_name, target_platform)
-    return FINNExampleOverlay(filename, driver_mode, _gtsrb_cnv_io_shape_dict)
+    return FINNExampleOverlay(filename, driver_mode, _gtsrb_cnv_io_shape_dict)