Merge pull request #91 from Xilinx/refactor/rtl_integration

Refactor all build flows to work with FINN v0.10
Xilinx · May 3, 2024 · f1dc4ef · f1dc4ef
2 parents e267e7b + e4e1c96
commit f1dc4ef
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diff --git a/AMD-license-agreement-for-non-commercial-models.md b/AMD-license-agreement-for-non-commercial-models.md
@@ -3,7 +3,7 @@ LICENSE AGREEMENT FOR NON-COMMERCIAL MODELS
 
 Trained Models:
 
-bincop-cnv, cnv-w1a1, cnv-w1a2, cnv-w2a2, kwsmlp-w3a3, mobilenetv1-w4a4, resnet50-w1a2, tfc-w1a1, tfc-w1a2, tfc-w2a2, unsw_nb15-mlp-w2a2, vgg10-radioml-w4a4
+bincop-cnv, cnv-w1a1, cnv-w1a2, cnv-w2a2, kwsmlp-w3a3, mobilenetv1-w4a4, resnet50-w1a2, tfc-w1a1, tfc-w1a2, tfc-w2a2, unsw_nb15-mlp-w2a2, vgg10-radioml-w4a4, cnv_1w1a_gtsrb.onnx
 
 This License Agreement for Non-Commercial Models (“Agreement”) is a legal agreement between you (either an individual or an entity) and Advanced Micro Devices, Inc. on behalf of itself and its subsidiaries and affiliates (collectively “AMD”). DO NOT USE THE TRAINED MODELS IDENTIFIED ABOVE UNTIL YOU HAVE CAREFULLY READ THIS AGREEMENT. BY USING, INSTALLING, MODIFYING, COPYING, TRAINING, BENCHMARKING, OR DISTRIBUTING THE TRAINED MODELS, YOU AGREE TO AND ACCEPT ALL TERMS AND CONDITIONS OF THIS AGREEMENT. If you do not accept these terms, do not use the Trained Models.
 

diff --git a/AUTHORS.rst b/AUTHORS.rst
@@ -2,9 +2,17 @@
 Contributors
 ============
 
-* Yaman Umuroglu (@maltanar) (maintainer)
+* Mirza Mrahorovic (@mmrahorovic) (maintainer)
 * Jakoba Petri-Koenig (@auphelia)
+* Yaman Umuroglu (@maltanar)
 * Lucian Petrica (@quetric)
 * Tobias Alonso (@Tobi-Alonso)
 * Hendrik Borras (@HenniOVP)
 * Felix Paul Jentzsch (@felixpj)
+* Aziz Bahri (@azizb-xlnx)
+* John Monks (@jmonks-amd)
+* Fionn O'Donohoe (@fionnodonohoe-xlnx)
+* Radoslav Pitoňák (@rpitonak)
+* Matthias Gehre (@mgehre-amd)
+* NaelF (@NaelF)
+* Tim Paine (@timkpaine)
diff --git a/LICENSE b/LICENSE
@@ -1,20 +1,22 @@
 BSD 3-Clause License
 
-Copyright (c) 2023, Xilinx
+Copyright (C) 2020-2022, Xilinx, Inc.
+Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are met:
 
-1. Redistributions of source code must retain the above copyright notice, this
-   list of conditions and the following disclaimer.
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
 
-2. Redistributions in binary form must reproduce the above copyright notice,
-   this list of conditions and the following disclaimer in the documentation
-   and/or other materials provided with the distribution.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
 
-3. Neither the name of the copyright holder nor the names of its
-   contributors may be used to endorse or promote products derived from
-   this software without specific prior written permission.
+* Neither the name of FINN nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
 
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

diff --git a/build/README.md b/build/README.md
@@ -16,7 +16,7 @@ to do this again in the future when the `finn-examples` repo gets updated and re
 Docker community edition `docker-ce`.
 
 3. Set up the environment variables to point to your Vivado/Vitis installation, depending on your target platform(s):
-    *  For Zynq platforms you'll need to set `VIVADO_PATH`, e.g. `VIVADO_PATH=/opt/xilinx/Vivado/2019.1/`
+    * For Zynq platforms you'll need to set `VIVADO_PATH`, e.g. `VIVADO_PATH=/opt/xilinx/Vivado/2022.2/`
     * For Alveo platforms you'll need to set `VITIS_PATH`, `PLATFORM_REPO_PATHS` and `XILINX_XRT`
 
 ## Build bitfiles

diff --git a/build/bnn-pynq/README.md b/build/bnn-pynq/README.md
@@ -42,7 +42,7 @@ cd $FINN_EXAMPLES/build/finn
 The BNN-PYNQ networks are part of the
 [Brevitas examples](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq). You can find the details on quantization, accuracy, layers used in the Brevitas repo, as well as the training scripts if you'd like to retrain them yourself.
 
-Subsequently, those trained networks are [exported to ONNX](https://github.com/Xilinx/finn/blob/master/notebooks/basics/1_brevitas_network_import.ipynb). In addition, the particular versions
+Subsequently, those trained networks are [exported to ONNX](https://github.com/Xilinx/finn/blob/main/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb). In addition, the particular versions
 used here have two additions, as described in the "Adding Pre- and Postprocessing" section of [this notebook](https://github.com/Xilinx/finn/blob/master/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb):
 
 * A divide-by-255 node is added at the input, and the input is marked as 8-bit (to directly accept 8-bit images as input)

diff --git a/build/bnn-pynq/build.py b/build/bnn-pynq/build.py
@@ -1,3 +1,31 @@
+# Copyright (C) 2024, Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+#   list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+#   this list of conditions and the following disclaimer in the documentation
+#   and/or other materials provided with the distribution.
+#
+# * Neither the name of FINN nor the names of its
+#   contributors may be used to endorse or promote products derived from
+#   this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
 import finn.builder.build_dataflow as build
 import finn.builder.build_dataflow_config as build_cfg
 from finn.util.basic import alveo_default_platform
@@ -54,12 +82,13 @@ def platform_to_shell(platform):
         cfg = build_cfg.DataflowBuildConfig(
             output_dir="output_%s_%s" % (model_name, release_platform_name),
             folding_config_file="folding_config/%s_folding_config.json" % model_name,
-            synth_clk_period_ns=10.0,
+            synth_clk_period_ns=5.0,
             board=platform_name,
             shell_flow_type=shell_flow_type,
             vitis_platform=vitis_platform,
             generate_outputs=[build_cfg.DataflowOutputType.BITFILE],
             save_intermediate_models=True,
+            default_swg_exception=True,
         )
         model_file = "models/%s.onnx" % model_name
         # launch FINN compiler to build

diff --git a/build/bnn-pynq/folding_config/cnv-w1a1_folding_config.json b/build/bnn-pynq/folding_config/cnv-w1a1_folding_config.json
@@ -1,79 +1,87 @@
 {
   "Defaults": {},
-  "Thresholding_Batch_0": {
-    "PE": 1,
-    "ram_style": "distributed"
+  "Thresholding_rtl_0": {
+    "PE": 1
   },
-  "ConvolutionInputGenerator_0": {
+  "ConvolutionInputGenerator_rtl_0": {
     "SIMD": 3,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_0": {
+  "MVAU_hls_0": {
     "PE": 16,
     "SIMD": 3,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_1": {
+  "ConvolutionInputGenerator_rtl_1": {
     "SIMD": 32,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_1": {
+  "MVAU_hls_1": {
     "PE": 32,
     "SIMD": 32,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_2": {
+  "ConvolutionInputGenerator_rtl_2": {
     "SIMD": 32,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_2": {
+  "MVAU_hls_2": {
     "PE": 16,
     "SIMD": 32,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_3": {
+  "ConvolutionInputGenerator_rtl_3": {
     "SIMD": 32,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_3": {
+  "MVAU_hls_3": {
     "PE": 16,
     "SIMD": 32,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_4": {
+  "ConvolutionInputGenerator_rtl_4": {
     "SIMD": 32,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_4": {
+  "MVAU_hls_4": {
     "PE": 4,
     "SIMD": 32,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_5": {
+  "ConvolutionInputGenerator_rtl_5": {
     "SIMD": 32,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_5": {
+  "MVAU_hls_5": {
     "PE": 1,
     "SIMD": 32,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_6": {
+  "MVAU_hls_6": {
     "PE": 1,
     "SIMD": 4,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_7": {
+  "MVAU_hls_7": {
     "PE": 1,
     "SIMD": 8,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_8": {
+  "MVAU_hls_8": {
     "PE": 5,
     "SIMD": 1,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "LabelSelect_Batch_0": {
+  "LabelSelect_hls_0": {
     "PE": 1
   }
 }
diff --git a/build/bnn-pynq/folding_config/cnv-w1a2_folding_config.json b/build/bnn-pynq/folding_config/cnv-w1a2_folding_config.json
@@ -1,79 +1,87 @@
 {
   "Defaults": {},
-  "Thresholding_Batch_0": {
-    "PE": 1,
-    "ram_style": "distributed"
+  "Thresholding_rtl_0": {
+    "PE": 1
   },
-  "ConvolutionInputGenerator_0": {
+  "ConvolutionInputGenerator_rtl_0": {
     "SIMD": 3,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_0": {
+  "MVAU_hls_0": {
     "PE": 8,
     "SIMD": 3,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_1": {
+  "ConvolutionInputGenerator_rtl_1": {
     "SIMD": 16,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_1": {
+  "MVAU_hls_1": {
     "PE": 16,
     "SIMD": 16,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_2": {
+  "ConvolutionInputGenerator_rtl_2": {
     "SIMD": 16,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_2": {
+  "MVAU_hls_2": {
     "PE": 8,
     "SIMD": 16,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_3": {
+  "ConvolutionInputGenerator_rtl_3": {
     "SIMD": 16,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_3": {
+  "MVAU_hls_3": {
     "PE": 8,
     "SIMD": 16,
-    "ram_style": "block"
+    "ram_style": "block",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_4": {
+  "ConvolutionInputGenerator_rtl_4": {
     "SIMD": 8,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_4": {
+  "MVAU_hls_4": {
     "PE": 4,
     "SIMD": 8,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "ConvolutionInputGenerator_5": {
+  "ConvolutionInputGenerator_rtl_5": {
     "SIMD": 8,
     "ram_style": "distributed"
   },
-  "MatrixVectorActivation_5": {
+  "MVAU_hls_5": {
     "PE": 1,
     "SIMD": 8,
-    "ram_style": "auto"
+    "ram_style": "auto",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_6": {
+  "MVAU_hls_6": {
     "PE": 1,
     "SIMD": 2,
-    "ram_style": "distributed"
+    "ram_style": "distributed",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_7": {
+  "MVAU_hls_7": {
     "PE": 2,
     "SIMD": 2,
-    "ram_style": "block"
+    "ram_style": "block",
+    "resType": "lut"
   },
-  "MatrixVectorActivation_8": {
+  "MVAU_hls_8": {
     "PE": 5,
     "SIMD": 1,
-    "ram_style": "distributed"
+    "ram_style": "distributed",
+    "resType": "lut"
   },
-  "LabelSelect_Batch_0": {
+  "LabelSelect_hls_0": {
     "PE": 1
   }
 }