Merge pull request #1170 from Xilinx/feature/v80

Add v80
Xilinx · Aug 22, 2024 · 33c4153 · 33c4153
2 parents 793656b + 380d2ac
commit 33c4153
Show file tree

Hide file tree

Showing 2 changed files with 8 additions and 5 deletions.
diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py
@@ -208,7 +208,10 @@ def _resolve_impl_style(self, dsp_block):
         weight_width = self.get_input_datatype(1).bitwidth()
 
         if dsp_block == "DSP58":
-            return "mvu_vvu_8sx9_dsp58"
+            if act_width <= 4 and weight_width <= 4:
+                return "mvu_4sx4u_dsp48e2"
+            else:
+                return "mvu_vvu_8sx9_dsp58"
         else:
             if act_width <= 4 and weight_width <= 4:
                 if dsp_block == "DSP48E1":

diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py
@@ -292,10 +292,10 @@ def memutil(req_mem_spec, primitive_spec):
 
 def is_versal(fpgapart):
     """Returns whether board is part of the Versal family"""
-    return (
-        fpgapart[0:4] in ["xcvc", "xcve", "xcvp", "xcvm", "xqvc", "xqvm"]
-        or fpgapart[0:5] == "xqrvc"
-    )
+    return fpgapart[0:4] in ["xcvc", "xcve", "xcvp", "xcvm", "xqvc", "xqvm"] or fpgapart[0:5] in [
+        "xqrvc",
+        "xcv80",
+    ]
 
 
 def get_dsp_block(fpgapart):