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Fix table row of the DSP48 post synthesis resource utilization report
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According to the last synthesis I ran using Vitis/Vivado 2022.2, the
DSP48 utilization seems to be reported in row 10 of the XML table.
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iksnagreb committed Apr 3, 2024
1 parent de1f024 commit b435655
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/finn/analysis/fpgadataflow/post_synth_res.py
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ def post_synth_res(model, override_synth_report_filename=None):
"FF": 6,
"BRAM_36K": 7,
"BRAM_18K": 8,
"DSP48": 9,
"DSP48": 10,
}
restype_to_ind_vitis = {
"LUT": 4,
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