Release merge for v0.10 #1024

auphelia · 2024-03-29T15:32:27Z

Refactored custom operator infrastructure + FINN flow
New RTL components
Improved accumulator width minimization and weight bit width minimization
Transposed Convolution
SELU support
Enablement of beta devices
Improved compatibility between tool versions for Zynq Build and additional boards for system integration flow
Revised memstream component
Additional tutorials:
- Tutorial about QONNX export and QONNX -> FINN-ONNX conversion
- Tutorial about Folding Factors
- Tutorial about Advanced Builder Settings

More details in release blog post coming soon.

…class hiearchy

This reverts commit c54d32c.

Refactoring of HLS MVAU/VVAU

Singularity container support for run script

VVAU renaming and disabled resType selection in convert-to-hw

Signed-off-by: auphelia <jakobapk@web.de>

…q-z1

…lection

RTL SWG CPPsim

[Tests] Force HLS components for special case cnv-2-2 on u250 and pyn…

Extract Thresholding RTL RAM trigger attributes to folding config

Refactoring of RTL/HLS component integration

…custom-ops)

VVU estimation function fixes

Minor fixes to documentation and examples for dev branch

mmrahorovic and others added 30 commits February 1, 2024 15:22

[transform]: add transformation to infer MVAU hw custom-op

627639a

[test mvau]: modified to support new custom-ops

cd3d431

[vvau hls]: add custom op to dict

0348a7c

[vvu hw-op]: refactored hw custom-op VVAU

b2c10d8

[vvau hls-op]: refactored HLS custom-op VVAU

f7d0ad9

[convert-to-hw]: added transformations to infer binary-MVAU and VVAU

f9b8fbc

[mvau/vvau hw-op]: remove duplicate node attribute

8be157c

[hw vvau]: rename specific method to more generic name

445cfa6

[hw vvau]: minor bugfix to node execution

e33104e

[test]: extend vvau test to simulate HW custom-op as well

6884030

[hw mvau]: minor bugfix to node execution and cleaned up code

8aaec4b

[test]: cleaned up mvau test

07f977e

[hw mvau]: minor bugfix

3466e88

updated copyright header

496869f

[hls vvau]: add execute_node function

2910aca

[CustomOp] re arrange threshold mem_mode related attributes to match …

b4fb604

…class hiearchy

[rtllib] Remove threshold IP Package

9ec0a3d

[CustomOp] do not allow ram_style for threshold RTL

3fd5260

Revert "[Pyverilator] update to new rtlsim_multi_io implementation"

c8281c3

This reverts commit c54d32c.

Merge pull request #971 from mmrahorovic/refactor/hls_mvu_vvu

7fd0cee

Refactoring of HLS MVAU/VVAU

[CustomOp] Thresholding node must explicitly reset_rtlsim

3f3b7c5

[CustomOp/Transform] Fix linting and cleanup

84ec9ea

[Tests] Disable lfc on Alveo and apply fix to driver_base

6986a8b

[Tests] Only disable lfc test for alveo during HW testing

1ee77b7

[Util] Introduce new functions to check if node is hls or rtl

05881df

[Tests] First cleanup over tests to update to new flow

94a2ff3

[CustomOp] Thresholding Generate Param

d24ef63

[Tests/transforms] Cleanup tests and transforms for new flow

c4b7b4b

Merge pull request #868 from fpjentzsch/feature/apptainer

04b9c9d

Singularity container support for run script

[Tests] Update infer data layout test

0fe2e30

auphelia and others added 28 commits March 25, 2024 11:40

Merge pull request #1012 from mmrahorovic/bugfix/vvau_renaming

6226ab5

VVAU renaming and disabled resType selection in convert-to-hw

[Docs] Update top level markdown files

e057fc9

Signed-off-by: auphelia <jakobapk@web.de>

[Docs] Fix typo in CONTRIBUTING markdown

7b13840

Signed-off-by: auphelia <jakobapk@web.de>

[Docs] Update AUTHORS md

d4fbd21

Signed-off-by: auphelia <jakobapk@web.de>

[Tests/Docs] Set SWG to HLS for depthwise conv cppsim tests

6d03694

[Deps] Update dockerfile with new copyright header

00e6e51

[Tests] Force HLS components for special case cnv-2-2 on u250 and pyn…

1e97e97

…q-z1

[rtl swg]: interleave channels for CPPsim

aa361f5

[vvau]: RTL-swg in cppsim now interleaves channels -- updated 'pe' se…

87d11c6

…lection

[tests]: remove defaulting SWG to HLS

42852df

Merge pull request #1014 from mmrahorovic/fix/rtl_swg_cppsim

61b27b4

RTL SWG CPPsim

[Tests] Enable interleaving of output for dw only

86e28e4

Merge pull request #1015 from Xilinx/testing/force_hls_cnv

cf8e9df

[Tests] Force HLS components for special case cnv-2-2 on u250 and pyn…

Fix linting

84654a3

[Thresholding RTL] extract RAM trigger to json config

9507e23

Merge pull request #1016 from Xilinx/bugfix/thresh_json

b9d4e62

Extract Thresholding RTL RAM trigger attributes to folding config

Merge pull request #928 from Xilinx/refactor/rtl_integration

68b1a6d

Refactoring of RTL/HLS component integration

[Docs] Update recommended Vivado/Vitis version

10fa01e

[vvau]: removed estimation methods for lut/dsp (moved to specialized …

dfd501e

…custom-ops)

[rtl vvau]: minor fix to dsp estimation

b84de7b

[hls vvau]: added lut and dsp estimation methods

ae97e38

[NBs] Fix referenced builder step in advanced nb

22de8a6

Merge pull request #1018 from mmrahorovic/hotfix/vvu_estimations

82faae7

VVU estimation function fixes

[Docs] Upgrade rtd requirements

1294eba

[Docs] Minor fixes in rtd documentation

769f81f

[Docs] Update build dataflow example folder

038d306

[Tests] Runtime writeable weights = 0 for RTL thresholding in tfc test

b318693

Merge pull request #1023 from Xilinx/fix/minor_fixes

766e9fb

Minor fixes to documentation and examples for dev branch

auphelia marked this pull request as ready for review April 2, 2024 10:43

auphelia merged commit e3087ad into main Apr 2, 2024
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Release merge for v0.10 #1024

Release merge for v0.10 #1024

auphelia commented Mar 29, 2024

Release merge for v0.10 #1024

Release merge for v0.10 #1024

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auphelia commented Mar 29, 2024