4-BIT DSP-MVU: Allow very wide lanes requiring even a high-lane extension. #1203
+2,941
−194
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This PR removes the assumption that the leftmost lane of a low-precision soft vector compute on the wide DSP datapath would. The design now also generates a high lane extension for the leftmost lane in the fabric as needed.
Additionally, the cross-SIMD reduction in an adder tree is now pipelined so as to reduce the challenge for timing closure in high-fanin designs.