Pyxsi enablement for alternative rtl simulation

docker/Dockerfile.finn

@@ -65,12 +65,18 @@ RUN apt-get update && \
     python-is-python3 \
     python3-pip \
     python3-setuptools-scm \
-    python3-venv
+    python3-venv \
+    pybind11-dev \
+    libfmt-dev \
+    libboost-dev \
+    libjansson-dev \
+    libgetdata-dev \
+    libtinfo5
 RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
 RUN locale-gen "en_US.UTF-8"
 
 # install Verilator from source to get the right version
-RUN apt-get install -y git perl make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev
+RUN apt-get install -y git perl make autoconf g++-10 flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev
 RUN git clone https://github.com/verilator/verilator
 RUN cd verilator && \
     git checkout v4.224 && \

docker/finn_entrypoint.sh

@@ -105,6 +105,21 @@ else
   fi
 fi
 
+if [ -z "${XILINX_VIVADO}" ]; then
+  yecho "pyxsi will be unavailable since Vivado was not found"
+else
+  if [ -f "${FINN_ROOT}/deps/pyxsi/pyxsi.so" ]; then
+    gecho "Found pyxsi at ${FINN_ROOT}/deps/pyxsi/pyxsi.so"
+  else
+    OLDPWD=$(pwd)
+    cd ${FINN_ROOT}/deps/pyxsi
+    touch .dockerenv
+    make
+    cd $OLDPWD
+  fi
+  export PYTHONPATH=$PYTHONPATH:${FINN_ROOT}/deps/pyxsi:${FINN_ROOT}/deps/pyxsi/py
+fi
+
 if [ -f "$HLS_PATH/settings64.sh" ];then
   # source Vitis HLS env.vars
   source $HLS_PATH/settings64.sh
@@ -129,6 +144,7 @@ if [ -d "$FINN_ROOT/.Xilinx" ]; then
     mkdir "$HOME/.Xilinx/Vivado/"
     cp "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" "$HOME/.Xilinx/Vivado/"
     gecho "Found Vivado_init.tcl and copied to $HOME/.Xilinx/Vivado/Vivado_init.tcl"
+
   else
     yecho "Unable to find $FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl"
   fi

fetch-repos.sh

@@ -39,6 +39,7 @@ XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
 RFSOC4x2_BDF_COMMIT="13fb6f6c02c7dfd7e4b336b18b959ad5115db696"
 KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79"
 EXP_BOARD_FILES_MD5="226ca927a16ea4ce579f1332675e9e9a"
+PYXSI_COMMIT="dc074bc1b3ecc2ab884531565d1aca6aa33ea5b9"
 
 QONNX_URL="https://github.com/fastmachinelearning/qonnx.git"
 FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git"
@@ -51,6 +52,7 @@ AVNET_BDF_URL="https://github.com/Avnet/bdf.git"
 XIL_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
 RFSOC4x2_BDF_URL="https://github.com/RealDigitalOrg/RFSoC4x2-BSP.git"
 KV260_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git"
+PYXSI_URL="https://github.com/maltanar/pyxsi.git"
 
 QONNX_DIR="qonnx"
 FINN_EXP_DIR="finn-experimental"
@@ -63,6 +65,7 @@ AVNET_BDF_DIR="avnet-bdf"
 XIL_BDF_DIR="xil-bdf"
 RFSOC4x2_BDF_DIR="rfsoc4x2-bdf"
 KV260_SOM_BDF_DIR="kv260-som-bdf"
+PYXSI_DIR="pyxsi"
 
 # absolute path to this script, e.g. /home/user/bin/foo.sh
 SCRIPT=$(readlink -f "$0")
@@ -126,6 +129,7 @@ fetch_repo $AVNET_BDF_URL $AVNET_BDF_COMMIT $AVNET_BDF_DIR
 fetch_repo $XIL_BDF_URL $XIL_BDF_COMMIT $XIL_BDF_DIR
 fetch_repo $RFSOC4x2_BDF_URL $RFSOC4x2_BDF_COMMIT $RFSOC4x2_BDF_DIR
 fetch_repo $KV260_BDF_URL $KV260_BDF_COMMIT $KV260_SOM_BDF_DIR
+fetch_repo $PYXSI_URL $PYXSI_COMMIT $PYXSI_DIR
 
 # Can skip downloading of board files entirely if desired
 if [ "$FINN_SKIP_BOARD_FILES" = "1" ]; then

notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb

@@ -404,6 +404,7 @@
     "child_model = child_model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))\n",
     "child_model = child_model.transform(PrepareRTLSim())\n",
     "child_model.set_metadata_prop(\"exec_mode\",\"rtlsim\")\n",
+    "child_model.set_metadata_prop(\"rtlsim_backend\",\"pyverilator\")\n",
     "child_model.save(build_dir + \"/tfc_w1_a1_dataflow_child.onnx\");"
    ]
   },

src/finn/builder/build_dataflow_steps.py

@@ -250,6 +250,8 @@ def prepare_for_stitched_ip_rtlsim(verify_model, cfg):
     # set top-level prop for stitched-ip rtlsim and launch
     verify_model.set_metadata_prop("exec_mode", "rtlsim")
     # TODO make configurable
+    verify_model.set_metadata_prop("rtlsim_backend", "pyverilator")
+    # TODO make configurable
     # verify_model.set_metadata_prop("rtlsim_trace", "trace.vcd")
     return verify_model
 

src/finn/core/onnx_exec.py

@@ -52,44 +52,38 @@ def execute_onnx(model, input_dict, return_full_exec_context=False, start_node=N
     model_exec_mode = model.get_metadata_prop("exec_mode")
     if (model_exec_mode is None) or (model_exec_mode == ""):
         return execute_onnx_base(model, input_dict, return_full_exec_context, start_node, end_node)
+    elif model_exec_mode == "rtlsim":
+        # check sanity of model and then use stitched IP for rtlsim
+        if not model.check_all_tensor_shapes_specified():
+            raise Exception("Found unspecified tensor shapes, try infer_shapes")
+        ret = model.analysis(ta.nodes_topologically_sorted)
+        assert (
+            ret["nodes_topologically_sorted"] is True
+        ), """Nodes must be
+        topologically sorted."""
 
-    if not model.check_all_tensor_shapes_specified():
-        raise Exception("Found unspecified tensor shapes, try infer_shapes")
-    ret = model.analysis(ta.nodes_topologically_sorted)
-    assert (
-        ret["nodes_topologically_sorted"] is True
-    ), """Nodes must be
-    topologically sorted."""
-
-    graph = model.graph
-    # first, we need to make sure that every variable required by the graph has
-    # some buffer associated with it. this includes graph inputs (which includes
-    # the input data as well as the trained parameters) and the graph ValueInfo
-    # (intermediate tensors between layers)
-    # this is provided by the execution_context, which is a dict of np.ndarray
-    execution_context = model.make_empty_exec_context()
-    # fill in any inputs provided to this function
-    for inp_name in input_dict.keys():
-        if inp_name in execution_context:
-            if execution_context[inp_name].shape == input_dict[inp_name].shape:
-                execution_context[inp_name] = input_dict[inp_name]
-            else:
-                raise Exception(
-                    "Shape mismatch for provided input %s: found %s expected %s "
-                    % (
-                        inp_name,
-                        str(execution_context[inp_name].shape),
-                        str(input_dict[inp_name].shape),
+        graph = model.graph
+        # first, we need to make sure that every variable required by the graph has
+        # some buffer associated with it. this includes graph inputs (which includes
+        # the input data as well as the trained parameters) and the graph ValueInfo
+        # (intermediate tensors between layers)
+        # this is provided by the execution_context, which is a dict of np.ndarray
+        execution_context = model.make_empty_exec_context()
+        # fill in any inputs provided to this function
+        for inp_name in input_dict.keys():
+            if inp_name in execution_context:
+                if execution_context[inp_name].shape == input_dict[inp_name].shape:
+                    execution_context[inp_name] = input_dict[inp_name]
+                else:
+                    raise Exception(
+                        "Shape mismatch for provided input %s: found %s expected %s "
+                        % (
+                            inp_name,
+                            str(execution_context[inp_name].shape),
+                            str(input_dict[inp_name].shape),
+                        )
                     )
-                )
 
-    # check if model has an execution mode set
-    # if None, execute model node by node using execute_node()
-    # if set to "rtlsim" execute model using pyverilator
-    model_exec_mode = model.get_metadata_prop("exec_mode")
-    if (model_exec_mode is None) or (model_exec_mode == ""):
-        return execute_onnx_base()
-    elif model_exec_mode == "rtlsim":
         # use stitched IP for rtlsim
         rtlsim_exec(model, execution_context)
     else: