Merge pull request #102 from Xilinx/ferdinand.allow_bf16_avgpool_tosa

Allow BF16 tosa.avgpool2d in verifiers
Xilinx · Feb 8, 2024 · 0ee5de7 · 0ee5de7
2 parents 53132a4 + 5e87840
commit 0ee5de7
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
@@ -193,6 +193,8 @@ LogicalResult tosa::AvgPool2dOp::verify() {
 
   if (inputETy.isF32() && resultETy.isF32())
     return success();
+  if (inputETy.isBF16() && resultETy.isBF16())
+    return success();
   if (inputETy.isInteger(8) && resultETy.isInteger(8))
     return success();
   if (inputETy.isInteger(16) && resultETy.isInteger(16))