Merge pull request #384 from Xilinx/matthias.trailing_semi_verbatim

Don't print semicolon after emitc.verbatim within emitc.for

mlir/lib/Target/Cpp/TranslateToCpp.cpp

@@ -1063,16 +1063,7 @@ static LogicalResult printFunctionBody(CppEmitter &emitter,
         return failure();
     }
     for (Operation &op : block.getOperations()) {
-      // When generating code for an emitc.if or cf.cond_br op no semicolon
-      // needs to be printed after the closing brace.
-      // When generating code for an emitc.for and emitc.verbatim op, printing a
-      // trailing semicolon is handled within the printOperation function.
-      bool trailingSemicolon =
-          !isa<cf::CondBranchOp, emitc::DeclareFuncOp, emitc::ForOp,
-               emitc::IfOp, emitc::VerbatimOp>(op);
-
-      if (failed(emitter.emitOperation(
-              op, /*trailingSemicolon=*/trailingSemicolon)))
+      if (failed(emitter.emitOperation(op, /*trailingSemicolon=*/true)))
         return failure();
     }
   }
@@ -1630,6 +1621,11 @@ LogicalResult CppEmitter::emitOperation(Operation &op, bool trailingSemicolon) {
        shouldBeInlined(cast<emitc::ExpressionOp>(op))))
     return success();
 
+  if (isa<cf::CondBranchOp, emitc::DeclareFuncOp, emitc::ForOp, emitc::IfOp,
+          emitc::VerbatimOp>(op)) {
+    trailingSemicolon = false;
+  }
+
   os << (trailingSemicolon ? ";\n" : "\n");
 
   return success();

mlir/test/Target/Cpp/verbatim.mlir

@@ -40,6 +40,18 @@ emitc.func @func(%arg: f32) {
 
   emitc.verbatim "#pragma my2 var={} property" %a : !emitc.array<3x7xi32>
   // CHECK-NEXT: #pragma my2 var=[[A]] property
+  emitc.return
+}
 
+// Check that no semicolon is printed after verbatim within emitc.for
+emitc.func @in_loop(%arg: f32) {
+  %start = emitc.literal "0" : !emitc.size_t
+  %stop = emitc.literal "10" : !emitc.size_t
+  %step = emitc.literal "1" : !emitc.size_t
+  emitc.for %iter = %start to %stop step %step {
+    emitc.verbatim "#pragma"
+     // CHECK: #pragma
+    emitc.yield
+  }
   emitc.return
 }