Bump e5ed7b6e2fd3 (Feb 27th) #134
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Mar 14, 2024
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mgehre-amd
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- Wait for onnx-mlir bump
… sides of branch The false branch for `and` and true branch for `or` provide less information (intersection as opposed to union), but still can give some useful information. Closes llvm#82818
…lvm#82929) This patch extends `reassociateMinMaxWithConstants` to fold the following patterns: ``` umax (smax X, nneg C0), nneg C1 --> smax X, (umax C0, C1) smin (umin X, nneg C0), nneg C1 --> umin X, (smin/umin C0, C1) ``` Alive2: https://alive2.llvm.org/ce/z/wfEj-e Address the comment llvm#82472 (review).
…llvm#82933) This reverts commit 691b12a.
When roundtripping to bytecode an unregistered operation name that does not contain any '.' separator, the bytecode writer will emit an op encoding without a proper opName. In this case, the string just becomes a possibly unknown dialect name. At parsing, this dialect name is used as a proper operation name. However, when the unregistered operation name coincidentally matches that of a dialect, the parser would fail. That means we can't roundtrip an unregistered op with a name that matches one of the registered dialect names. For example, ``` "index"() : () -> () ``` can be emitted but cannot be parsed, because its name is coincidentally the same as that of the Index dialect. The patch removes such inconsistency. This patch specifically fixes the bytecode roundtrip of `mlir/test/IR/parser.mlir`.
This enables to correctly roundtrip the attribute to text or bytecode.
…lvm#81552) Since ODS generates getters functions for SPIRV operations' attribute names, we replace instances of these hardcoded strings in the SPIR-V dialect's op parser/printer with function calls for consistency. Fixes llvm#77627 --------- Co-authored-by: Lei Zhang <antiagainst@gmail.com>
…izeROCDLTarget.cpp (NFC)
…izeToLLVMBitcode.cpp (NFC)
…g X), X) (llvm#79417) This is useful when computing absdiff. Correctness prove: https://alive2.llvm.org/ce/z/eMbxps, https://alive2.llvm.org/ce/z/SNCWJe. --------- Co-authored-by: Yingwei Zheng <dtcxzyw@qq.com>
This commit updates the pattern matching logic for the `AddLike` predicate in `LoongArchInstrInfo.td` to use the `isBaseWithConstantOffset` function provided by `CurDAG`. This optimization aims to improve the efficiency of pattern matching by identifying cases where the operation can be represented as a base address plus a constant offset, which can lead to more efficient code generation.
This is a preparation of incoming Clang changes (llvm#82448) and just checks `TVIdx` is calculated correctly. NFC. `TVIdxBuilder` calculates deterministic Indices for each Condition Node. It is used for `clang` to emit `TestVector` indices (aka ID) and for `llvm-cov` to reconstruct `TestVectors`. This includes the unittest `CoverageMappingTest.TVIdxBuilder`. See also https://discourse.llvm.org/t/rfc-coverage-new-algorithm-and-file-format-for-mc-dc/76798
std::string was used here, likely by mistake. The usual convention for attributes is to use StringAttr.
…lvm#82902) Currently the DecoderEmitter spends a fair amount of cycles performing repeated linear walks over the entire instruction list. This patch eliminates one such walk during HwMode collection for EncodingInfos. The eliminated traversal visits every instruction and then every EncodingInfos entry for that instruction merely to collect all referenced HwModes. That information already happens to be present in the HwModeSelects created during the one-time construction of CodeGenHwModes. We instead traverse the HwModeSelects, collecting each one referenced as an encoding select. This set is a small constant in size and does not generally grow with the size of the instruction set.
Implement constexpr checking for null pointers being passed to arguments annotated as nonnull.
- Introduce `createDecision(E)` for the root node of `VisitBin`. - Handle `mcdc::DecisionParameters` for each Decision method.
… intrinsic with a overflowing binary operator (llvm#82935) Alive2: https://alive2.llvm.org/ce/z/gyL7mn Fixes llvm#82884.
Either LHS or RHS might be non-complex, but not both.
This reduces some lines.
RISC-V implements vector lrint/llrint by vfcvt.x.f.v.
This is also what the current interpreter does and a couple of test cases expect that.
…s. (llvm#82617) This uses a more systematic approach for determining whcich `DeclRefExpr`s mutate the underlying object: Instead of using a few matchers, we walk up the AST until we find a parent that we can prove cannot change the underlying object. This allows us to handle most address taking and dereference, bindings to value and const& variables, and track constness of pointee (see changes in DeclRefExprUtilsTest.cpp). This allows supporting more patterns in `performance-unnecessary-copy-initialization`. Those two patterns are relatively common: ``` const auto e = (*vector_ptr)[i] ``` and ``` const auto e = vector_ptr->at(i); ``` In our codebase, we have around 25% additional findings from `performance-unnecessary-copy-initialization` with this change. I did not see any additional false positives.
Enables conversion between llvm.dbg.label and DPLabel.
….bump_282d50147628
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commit e5ed7b6 Author: rohit-rao <rohitrao@google.com> Date: Tue Feb 27 15:23:00 2024 -0500 [clang] Extend define-target-os-macros to support XROS. (llvm#82833)
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ttjost
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Mar 20, 2024
…rns (llvm#82770)" This reverts commit a3c8ffb.
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