Merge branch 'Xilinx:main' into 1171-improve-type-constraints-for-aie…

…vecmul_elem-and-co

include/aie-c/TargetModel.h

@@ -0,0 +1,143 @@
+//===- TargetModel.h --------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2024 Advanced Micro Devices, Inc.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef AIE_C_TARGETMODEL_H
+#define AIE_C_TARGETMODEL_H
+
+#include "mlir-c/IR.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//===----------------------------------------------------------------------===//
+// Opaque type declarations.
+//
+// Types are exposed to C bindings as structs containing opaque pointers. They
+// are not supposed to be inspected from C. This allows the underlying
+// representation to change without affecting the API users. The use of structs
+// instead of typedefs enables some type safety as structs are not implicitly
+// convertible to each other.
+//
+// Instances of these types may or may not own the underlying object. The
+// ownership semantics is defined by how an instance of the type was obtained.
+//===----------------------------------------------------------------------===//
+
+#define DEFINE_C_API_STRUCT(name, storage)                                     \
+  struct name {                                                                \
+    storage d;                                                                 \
+  };                                                                           \
+  typedef struct name name
+
+DEFINE_C_API_STRUCT(AieTargetModel, uint32_t);
+
+#undef DEFINE_C_API_STRUCT
+
+MLIR_CAPI_EXPORTED AieTargetModel aieGetTargetModel(uint32_t device);
+
+/// Returns the number of columns in the target model.
+MLIR_CAPI_EXPORTED int aieTargetModelColumns(AieTargetModel targetModel);
+
+/// Returns the number of rows in the target model.
+MLIR_CAPI_EXPORTED int aieTargetModelRows(AieTargetModel targetModel);
+
+/// Returns true if this is an NPU target model.
+MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsCoreTile(AieTargetModel targetModel,
+                                                 int col, int row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsMemTile(AieTargetModel targetModel,
+                                                int col, int row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel,
+                                                    int col, int row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsShimPLTile(AieTargetModel targetModel,
+                                                   int col, int row);
+
+MLIR_CAPI_EXPORTED bool
+aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col, int row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsInternal(AieTargetModel targetModel,
+                                                 int src_col, int src_row,
+                                                 int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsWest(AieTargetModel targetModel,
+                                             int src_col, int src_row,
+                                             int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsEast(AieTargetModel targetModel,
+                                             int src_col, int src_row,
+                                             int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsNorth(AieTargetModel targetModel,
+                                              int src_col, int src_row,
+                                              int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsSouth(AieTargetModel targetModel,
+                                              int src_col, int src_row,
+                                              int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsMemWest(AieTargetModel targetModel,
+                                                int src_col, int src_row,
+                                                int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsMemEast(AieTargetModel targetModel,
+                                                int src_col, int src_row,
+                                                int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsMemNorth(AieTargetModel targetModel,
+                                                 int src_col, int src_row,
+                                                 int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool aieTargetModelIsMemSouth(AieTargetModel targetModel,
+                                                 int src_col, int src_row,
+                                                 int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED bool
+aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col,
+                                 int src_row, int dst_col, int dst_row);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetLocalMemorySize(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetNumLocks(AieTargetModel targetModel, int col, int row);
+
+MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel,
+                                                    int col, int row);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetNumMemTileRows(AieTargetModel targetModel);
+
+MLIR_CAPI_EXPORTED uint32_t
+aieTargetModelGetMemTileSize(AieTargetModel targetModel);
+
+/// Returns true if this is an NPU target model.
+MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AIE_C_TARGETMODEL_H

include/aie/Dialect/AIE/IR/AIEDialect.h

@@ -234,6 +234,7 @@ typedef struct DMAChannel {
 } DMAChannel;
 
 const AIETargetModel &getTargetModel(mlir::Operation *op);
+const AIETargetModel &getTargetModel(AIEDevice device);
 
 mlir::ParseResult
 parseObjectFifoProducerTile(mlir::OpAsmParser &parser,

include/aie/Dialect/AIE/IR/AIETargetModel.h

@@ -54,7 +54,7 @@ using TileID = struct TileID {
 
 class AIETargetModel {
 public:
-  AIETargetModel() = default;
+  AIETargetModel(AIEDevice device) : device(device) {}
 
   virtual ~AIETargetModel();
 
@@ -204,11 +204,17 @@ class AIETargetModel {
   // Return true if this is an NPU-based device
   // There are several special cases for handling the NPU at the moment.
   virtual bool isNPU() const { return false; }
+
+  // Return the AIEDevice for this target model
+  AIEDevice getDevice() const { return device; }
+
+private:
+  AIEDevice device;
 };
 
 class AIE1TargetModel : public AIETargetModel {
 public:
-  AIE1TargetModel() = default;
+  AIE1TargetModel(AIEDevice device) : AIETargetModel(device) {}
 
   bool isCoreTile(int col, int row) const override { return row > 0; }
   bool isMemTile(int col, int row) const override { return false; }
@@ -272,7 +278,7 @@ class AIE1TargetModel : public AIETargetModel {
 
 class AIE2TargetModel : public AIETargetModel {
 public:
-  AIE2TargetModel() = default;
+  AIE2TargetModel(AIEDevice device) : AIETargetModel(device) {}
 
   AIEArch getTargetArch() const override;
 
@@ -329,7 +335,7 @@ class VC1902TargetModel : public AIE1TargetModel {
       2, 3, 6, 7, 10, 11, 18, 19, 26, 27, 34, 35, 42, 43, 46, 47};
 
 public:
-  VC1902TargetModel() = default;
+  VC1902TargetModel(AIEDevice device) : AIE1TargetModel(device) {}
 
   int columns() const override { return 50; }
 
@@ -352,7 +358,7 @@ class VE2302TargetModel : public AIE2TargetModel {
   llvm::SmallDenseSet<unsigned, 8> nocColumns = {2, 3, 6, 7, 10, 11};
 
 public:
-  VE2302TargetModel() = default;
+  VE2302TargetModel(AIEDevice device) : AIE2TargetModel(device) {}
 
   int columns() const override { return 17; }
 
@@ -404,7 +410,7 @@ class VE2802TargetModel : public AIE2TargetModel {
                                                   22, 23, 30, 31, 34, 35};
 
 public:
-  VE2802TargetModel() = default;
+  VE2802TargetModel(AIEDevice device) : AIE2TargetModel(device) {}
 
   int columns() const override { return 38; }
 
@@ -456,7 +462,7 @@ class VE2802TargetModel : public AIE2TargetModel {
 
 class BaseNPUTargetModel : public AIE2TargetModel {
 public:
-  BaseNPUTargetModel() = default;
+  BaseNPUTargetModel(AIEDevice device) : AIE2TargetModel(device) {}
 
   int rows() const override {
     return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */
@@ -488,7 +494,7 @@ class BaseNPUTargetModel : public AIE2TargetModel {
 // The full Phoenix NPU
 class NPUTargetModel : public BaseNPUTargetModel {
 public:
-  NPUTargetModel() = default;
+  NPUTargetModel(AIEDevice device) : BaseNPUTargetModel(device) {}
 
   int columns() const override { return 5; }
 
@@ -509,7 +515,8 @@ class VirtualizedNPUTargetModel : public BaseNPUTargetModel {
   int cols;
 
 public:
-  VirtualizedNPUTargetModel(int _cols) : BaseNPUTargetModel(), cols(_cols) {}
+  VirtualizedNPUTargetModel(AIEDevice device, int _cols)
+      : BaseNPUTargetModel(device), cols(_cols) {}
 
   int columns() const override { return cols; }
 

include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td

@@ -15,6 +15,7 @@
 #define AIE_DIALECT_XLLVM_IR_XLLVMAIE2INTROPS_TD
 
 include "aie/Dialect/XLLVM/IR/XLLVM.td"
+include "aie/Dialect/XLLVM/IR/XLLVMTypeConstraints.td"
 include "mlir/Interfaces/InferTypeOpInterface.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
@@ -338,4 +339,16 @@ def VectorExtractElem32I512IntrOp :
                    I32:$idx,
                    I32:$sign)>;
 
+// ----- MAX ELEMENT -----
+
+def VectorMaxLtBf16IntrOp :
+    AIEVec2_IntrOp<"vmax.ltbf16",
+        [TypeIs<"res",
+            LLVM_StructOf<[
+                VectorOfLengthAndType<[32], [BF16]>,
+                I32]>
+        >], /*numResults=*/2>,
+    Arguments<(ins VectorOfLengthAndType<[32], [BF16]>:$lhs,
+                   VectorOfLengthAndType<[32], [BF16]>:$rhs)>;
+
 #endif // AIE_DIALECT_XLLVM_IR_XLLVMAIE2INTROPS_TD

include/aie/Dialect/XLLVM/IR/XLLVMTypeConstraints.td

@@ -0,0 +1,46 @@
+//===- XLLVMTypeConstraints.td - XLLVM type constraints. --*- tablegen -*-====//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2024 Advanced Micro Devices, Inc.
+//
+//===----------------------------------------------------------------------===//
+// Defines type constraints for LLVM types used in XLLVM intrinsic op
+// definitions.
+//===----------------------------------------------------------------------===//
+
+
+#ifndef AIE_DIALECT_XLLVM_IR_XLLVMTYPECONSTRAINTS_TD
+#define AIE_DIALECT_XLLVM_IR_XLLVMTYPECONSTRAINTS_TD
+
+class EnumeratedType<Type ty, int idx> {
+    Type type = ty;
+    int index = idx;
+}
+
+class EnumerateTypeListFrom<list<Type> tlist, int from = 0> {
+    list<EnumeratedType> sequence =
+        !if(!empty(tlist), [],
+            !listconcat(
+                    [EnumeratedType<!head(tlist), from>],
+                    EnumerateTypeListFrom<!tail(tlist), !add(from, 1)>.sequence
+                    ));
+}
+
+class LLVM_StructOf<list<Type> structTypes> :
+    Type<
+        And<[LLVM_AnyStruct.predicate,
+            CPred<"cast<::mlir::LLVM::LLVMStructType>($_self).getBody().size() == " # !size(structTypes)>,
+            And<!foreach(enumTy, EnumerateTypeListFrom<structTypes>.sequence,
+                SubstLeaves<"$_self",
+                    "cast<::mlir::LLVM::LLVMStructType>($_self).getBody()[" # enumTy.index # "]",
+                    enumTy.type.predicate>
+                )
+            >
+        ]>,
+        "an LLVM struct of {" # !interleave(!foreach(ty, structTypes, ty.summary), "; ") # "}"
+    >;
+
+#endif // AIE_DIALECT_XLLVM_IR_XLLVMTYPECONSTRAINTS_TD

lib/CAPI/CMakeLists.txt

@@ -4,6 +4,7 @@
 add_mlir_public_c_api_library(AIECAPI
   Dialects.cpp
   Registration.cpp
+  TargetModel.cpp
   Translation.cpp
 
   LINK_LIBS PUBLIC