Add IPU to TargetModel (#715)

Xilinx · Nov 3, 2023 · 0c2e176 · 0c2e176
1 parent 3429ee6
commit 0c2e176
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Showing 3 changed files with 53 additions and 1 deletion.
diff --git a/include/aie/Dialect/AIE/IR/AIEInterfaces.td b/include/aie/Dialect/AIE/IR/AIEInterfaces.td
@@ -158,6 +158,7 @@ def AIE2: I32EnumAttrCase<"AIE2", 2>;
 def xcvc1902: I32EnumAttrCase<"xcvc1902", 1>;
 def xcve2302: I32EnumAttrCase<"xcve2302", 2>;
 def xcve2802: I32EnumAttrCase<"xcve2802", 3>;
+def ipu: I32EnumAttrCase<"ipu", 4>;
 
 def LockAction: I32EnumAttr<"LockAction", "lock acquire/release",
   [Acquire, AcquireGreaterEqual, Release]> {
@@ -176,7 +177,7 @@ def AIEArch: I32EnumAttr<"AIEArch", "AIE Architecture",
   let cppNamespace = "xilinx::AIE";
 }
 def AIEDevice: I32EnumAttr<"AIEDevice", "AIE Device",
-  [xcvc1902, xcve2302, xcve2802]> {
+  [xcvc1902, xcve2302, xcve2802, ipu]> {
 
   let cppNamespace = "xilinx::AIE";
 }

diff --git a/include/aie/Dialect/AIE/IR/AIETargetModel.h b/include/aie/Dialect/AIE/IR/AIETargetModel.h
@@ -399,6 +399,54 @@ class VE2802TargetModel : public AIE2TargetModel {
   }
 };
 
+class IPUTargetModel : public AIE2TargetModel {
+  llvm::SmallDenseSet<unsigned, 16> noc_columns = {0, 1, 2, 3};
+
+public:
+  IPUTargetModel() {}
+
+  int columns() const override { return 5; }
+  int rows() const override {
+    return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */
+  }
+
+  bool isCoreTile(int col, int row) const override { return row > 1; }
+  bool isMemTile(int col, int row) const override { return row == 1; }
+
+  bool isShimNOCTile(int col, int row) const override {
+    return row == 0 && noc_columns.contains(col);
+  }
+  bool isShimPLTile(int col, int row) const override {
+    return row == 0 && !noc_columns.contains(col);
+  }
+  bool isShimNOCorPLTile(int col, int row) const override {
+    return isShimNOCTile(col, row) || isShimPLTile(col, row);
+  }
+  uint32_t getNumMemTileRows() const override { return 1; }
+  bool isValidTraceMaster(int col, int row, WireBundle destBundle,
+                          int destIndex) const override {
+    if (isCoreTile(col, row) && destBundle == WireBundle::South)
+      return true;
+    else if (isCoreTile(col, row) && destBundle == WireBundle::DMA &&
+             destIndex == 0)
+      return true;
+    else if (isMemTile(col, row) && destBundle == WireBundle::South)
+      return true;
+    else if (isMemTile(col, row) && destBundle == WireBundle::DMA &&
+             destIndex == 5)
+      return true;
+    else if (isShimNOCorPLTile(col, row) && destBundle == WireBundle::South)
+      return true;
+    else if (isShimNOCorPLTile(col, row) && destBundle == WireBundle::West &&
+             destIndex == 0)
+      return true;
+    else if (isShimNOCorPLTile(col, row) && destBundle == WireBundle::East &&
+             destIndex == 0)
+      return true;
+    return false;
+  }
+};
+
 } // namespace AIE
 } // namespace xilinx
 

diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp
@@ -74,6 +74,7 @@ namespace AIE {
 static xilinx::AIE::VC1902TargetModel VC1902model;
 static xilinx::AIE::VE2302TargetModel VE2302model;
 static xilinx::AIE::VE2802TargetModel VE2802model;
+static xilinx::AIE::IPUTargetModel IPUmodel;
 
 const xilinx::AIE::AIETargetModel &getTargetModel(Operation *op) {
   if (auto t = dyn_cast<xilinx::AIE::AIETarget>(op))
@@ -842,6 +843,8 @@ const xilinx::AIE::AIETargetModel &xilinx::AIE::DeviceOp::getTargetModel() {
     return VE2302model;
   case AIEDevice::xcve2802:
     return VE2802model;
+  case AIEDevice::ipu:
+    return IPUmodel;
   }
   return VC1902model;
 }