Change lower-cascade-flows tests to use check-dag (#1585)

Xilinx · Jun 28, 2024 · 218d6e6 · 218d6e6
1 parent 54efffa
commit 218d6e6
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Showing 2 changed files with 14 additions and 14 deletions.
diff --git a/test/lower-cascade-flows/cascade_single_flow.mlir b/test/lower-cascade-flows/cascade_single_flow.mlir
@@ -12,14 +12,14 @@
 
 // CHECK: module @cascade_flow {
 // CHECK:   aie.device(xcve2802) {
-// CHECK:     %tile_1_3 = aie.tile(1, 3)
-// CHECK:     %tile_2_3 = aie.tile(2, 3)
-// CHECK:     %tile_3_4 = aie.tile(3, 4)
-// CHECK:     %tile_3_3 = aie.tile(3, 3)
-// CHECK:     aie.configure_cascade(%tile_1_3, North, East)
-// CHECK:     aie.configure_cascade(%tile_2_3, West, South)
-// CHECK:     aie.configure_cascade(%tile_3_4, North, South)
-// CHECK:     aie.configure_cascade(%tile_3_3, North, South)
+// CHECK-DAG:     %tile_1_3 = aie.tile(1, 3)
+// CHECK-DAG:     %tile_2_3 = aie.tile(2, 3)
+// CHECK-DAG:     %tile_3_4 = aie.tile(3, 4)
+// CHECK-DAG:     %tile_3_3 = aie.tile(3, 3)
+// CHECK-DAG:     aie.configure_cascade(%tile_1_3, North, East)
+// CHECK-DAG:     aie.configure_cascade(%tile_2_3, West, South)
+// CHECK-DAG:     aie.configure_cascade(%tile_3_4, North, South)
+// CHECK-DAG:     aie.configure_cascade(%tile_3_3, North, South)
 // CHECK:   }
 // CHECK: }
 

diff --git a/test/lower-cascade-flows/cascade_two_flows.mlir b/test/lower-cascade-flows/cascade_two_flows.mlir
@@ -12,12 +12,12 @@
 
 // CHECK: module @cascade_flow {
 // CHECK:   aie.device(xcve2802) {
-// CHECK:     %tile_1_4 = aie.tile(1, 4)
-// CHECK:     %tile_2_4 = aie.tile(2, 4)
-// CHECK:     %tile_3_4 = aie.tile(3, 4)
-// CHECK:     aie.configure_cascade(%tile_1_4, North, East)
-// CHECK:     aie.configure_cascade(%tile_2_4, West, East)
-// CHECK:     aie.configure_cascade(%tile_3_4, West, South)
+// CHECK-DAG:     %tile_1_4 = aie.tile(1, 4)
+// CHECK-DAG:     %tile_2_4 = aie.tile(2, 4)
+// CHECK-DAG:     %tile_3_4 = aie.tile(3, 4)
+// CHECK-DAG:     aie.configure_cascade(%tile_1_4, North, East)
+// CHECK-DAG:     aie.configure_cascade(%tile_2_4, West, East)
+// CHECK-DAG:     aie.configure_cascade(%tile_3_4, West, South)
 // CHECK:   }
 // CHECK: }