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[aievec] to-llvm flow for aievec.shift op (#1432)
* Add vshift and vextract.elem intrinsic ops to XLLVM dialect. * Add aievec-to-llvm conversion pattern/tests for the aievec.shift op. * Add target external llvm translation tests. * Update test/unit_tests/aievec_tests/bf16_max_reduce e2e test and mark to-llvm test as XFAIL for now. * Other minor changes: add a f32 mul_elem scalar test, and a missing aievec.broadcast_scalar conversion test
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| // RUN: aie-opt %s -split-input-file -convert-aievec-to-llvm | FileCheck %s | ||
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| // ----- | ||
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| func.func @i8_shift(%arg0 : vector<64xi8>, %shift : i32) -> vector<64xi8> { | ||
| %0 = aievec.shift %arg0, %arg0, %shift {isAcc = false} : vector<64xi8>, vector<64xi8>, i32, vector<64xi8> | ||
| return %0 : vector<64xi8> | ||
| } | ||
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| // CHECK-LABEL: @i8_shift | ||
| // CHECK-SAME: %[[ARG0:.*]]: vector<64xi8>, | ||
| // CHECK-SAME: %[[SHIFT:.*]]: i32 | ||
| // CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 | ||
| // CHECK-NEXT: %[[BITCAST0:.*]] = llvm.bitcast %[[ARG0]] : vector<64xi8> to vector<16xi32> | ||
| // CHECK-NEXT: %[[BITCAST1:.*]] = llvm.bitcast %[[ARG0]] : vector<64xi8> to vector<16xi32> | ||
| // CHECK-NEXT: %[[VSHIFT:.*]] = "xllvm.intr.aie2.vshift.I512.I512"( | ||
| // CHECK-SAME: %[[BITCAST0]], %[[BITCAST1]], %[[CST]], %[[SHIFT]]) : | ||
| // CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32, i32) -> vector<16xi32> | ||
| // CHECK-NEXT: %[[RES:.*]] = llvm.bitcast %[[VSHIFT]] : vector<16xi32> to vector<64xi8> | ||
| // CHECK-NEXT: return %[[RES]] : vector<64xi8> | ||
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| // ----- | ||
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| func.func @i16_shift(%arg0 : vector<32xi16>, %shift : i32) -> vector<32xi16> { | ||
| %0 = aievec.shift %arg0, %arg0, %shift {isAcc = false} : vector<32xi16>, vector<32xi16>, i32, vector<32xi16> | ||
| return %0 : vector<32xi16> | ||
| } | ||
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| // CHECK-LABEL: @i16_shift | ||
| // CHECK-SAME: %[[ARG0:.*]]: vector<32xi16>, | ||
| // CHECK-SAME: %[[SHIFT:.*]]: i32 | ||
| // CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 | ||
| // CHECK-NEXT: %[[BITCAST0:.*]] = llvm.bitcast %[[ARG0]] : vector<32xi16> to vector<16xi32> | ||
| // CHECK-NEXT: %[[BITCAST1:.*]] = llvm.bitcast %[[ARG0]] : vector<32xi16> to vector<16xi32> | ||
| // CHECK-NEXT: %[[VSHIFT:.*]] = "xllvm.intr.aie2.vshift.I512.I512"( | ||
| // CHECK-SAME: %[[BITCAST0]], %[[BITCAST1]], %[[CST]], %[[SHIFT]]) : | ||
| // CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32, i32) -> vector<16xi32> | ||
| // CHECK-NEXT: %[[RES:.*]] = llvm.bitcast %[[VSHIFT]] : vector<16xi32> to vector<32xi16> | ||
| // CHECK-NEXT: return %[[RES]] : vector<32xi16> | ||
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| // ----- | ||
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| func.func @i32_shift(%arg0 : vector<16xi32>, %shift : i32) -> vector<16xi32> { | ||
| %0 = aievec.shift %arg0, %arg0, %shift {isAcc = false} : vector<16xi32>, vector<16xi32>, i32, vector<16xi32> | ||
| return %0 : vector<16xi32> | ||
| } | ||
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| // CHECK-LABEL: @i32_shift | ||
| // CHECK-SAME: %[[ARG0:.*]]: vector<16xi32>, | ||
| // CHECK-SAME: %[[SHIFT:.*]]: i32 | ||
| // CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 | ||
| // CHECK-NEXT: %[[VSHIFT:.*]] = "xllvm.intr.aie2.vshift.I512.I512"( | ||
| // CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]], %[[SHIFT]]) : | ||
| // CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32, i32) -> vector<16xi32> | ||
| // CHECK-NEXT: %[[RES:.*]] = llvm.bitcast %[[VSHIFT]] : vector<16xi32> to vector<16xi32> | ||
| // CHECK-NEXT: return %[[RES]] : vector<16xi32> | ||
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| // ----- | ||
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| func.func @bf16_shift(%arg0 : vector<32xbf16>, %shift : i32) -> vector<32xbf16> { | ||
| %0 = aievec.shift %arg0, %arg0, %shift {isAcc = false} : vector<32xbf16>, vector<32xbf16>, i32, vector<32xbf16> | ||
| return %0 : vector<32xbf16> | ||
| } | ||
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| // CHECK-LABEL: @bf16_shift | ||
| // CHECK-SAME: %[[ARG0:.*]]: vector<32xbf16>, | ||
| // CHECK-SAME: %[[SHIFT:.*]]: i32 | ||
| // CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 | ||
| // CHECK-NEXT: %[[VSHIFT:.*]] = "xllvm.intr.aie2.vshift.bf512.bf512"( | ||
| // CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]], %[[SHIFT]]) : | ||
| // CHECK-SAME: (vector<32xbf16>, vector<32xbf16>, i32, i32) -> vector<32xbf16> | ||
| // CHECK-NEXT: %[[RES:.*]] = llvm.bitcast %[[VSHIFT]] : vector<32xbf16> to vector<32xbf16> | ||
| // CHECK-NEXT: return %[[RES]] : vector<32xbf16> |
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29 changes: 29 additions & 0 deletions
29
test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce-llvm.mlir
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,29 @@ | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // Copyright (C) 2024, Advanced Micro Devices, Inc. | ||
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| // REQUIRES: valid_xchess_license | ||
| // REQUIRES: peano | ||
| // RUN: mkdir -p %t/data; cd %t | ||
| // RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir | ||
| // RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll | ||
| // RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o | ||
| // RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o | ||
| // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout | ||
| // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s | ||
| // CHECK: TEST PASSED | ||
| // XFAIL: * | ||
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| module { | ||
| func.func @dut(%arg0: memref<1024xbf16>, %arg1: memref<bf16>) { | ||
| %cst_0 = arith.constant dense<0xFF80> : vector<32xbf16> | ||
| %0 = affine.for %arg2 = 0 to 1024 step 32 iter_args(%arg3 = %cst_0) -> (vector<32xbf16>) { | ||
| %cst_1 = arith.constant 0.000000e+00 : bf16 | ||
| %3 = vector.transfer_read %arg0[%arg2], %cst_1 : memref<1024xbf16>, vector<32xbf16> | ||
| %4 = arith.maximumf %arg3, %3 : vector<32xbf16> | ||
| affine.yield %4 : vector<32xbf16> | ||
| } | ||
| %1 = vector.reduction <maximumf>, %0 : vector<32xbf16> into bf16 | ||
| affine.store %1, %arg1[] : memref<bf16> | ||
| return | ||
| } | ||
| } |
10 changes: 7 additions & 3 deletions
10
test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir
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29 changes: 29 additions & 0 deletions
29
test/unit_tests/aievec_tests/floatxfloat_mul_elem/floatxfloat_mul_elem-llvm-scalar.mlir
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,29 @@ | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // Copyright (C) 2024, Advanced Micro Devices, Inc. | ||
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| // REQUIRES: valid_xchess_license | ||
| // REQUIRES: peano | ||
| // RUN: mkdir -p %t/data; cd %t | ||
| // RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir | ||
| // RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll | ||
| // RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o | ||
| // RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o | ||
| // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout | ||
| // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s | ||
| // CHECK: TEST PASSED | ||
| // XFAIL: * | ||
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| module { | ||
| func.func @dut(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>, %arg2: memref<1024xf32>) { | ||
| memref.assume_alignment %arg0, 32 : memref<1024xf32> | ||
| memref.assume_alignment %arg1, 32 : memref<1024xf32> | ||
| memref.assume_alignment %arg2, 32 : memref<1024xf32> | ||
| affine.for %arg3 = 0 to 1024 { | ||
| %0 = affine.load %arg0[%arg3] : memref<1024xf32> | ||
| %1 = affine.load %arg1[%arg3] : memref<1024xf32> | ||
| %2 = arith.mulf %0, %1 : f32 | ||
| affine.store %2, %arg2[%arg3] : memref<1024xf32> | ||
| } | ||
| return | ||
| } | ||
| } |
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