[aievec] add I8/I16/I32 reduce + aievec.min/max e2e to-llvm tests (#1569

)

test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce-llvm.mlir

@@ -4,7 +4,6 @@
 // REQUIRES: valid_xchess_license
 // REQUIRES: peano
 // RUN: mkdir -p %t/data; cd %t
-// RUN: aie-opt %s %vector-to-aievec% -o aievec.mlir
 // RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
 // RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
 // RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o

test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce-llvm.mlir

@@ -4,7 +4,6 @@
 // REQUIRES: valid_xchess_license
 // REQUIRES: peano
 // RUN: mkdir -p %t/data; cd %t
-// RUN: aie-opt %s %vector-to-aievec% -o aievec.mlir
 // RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
 // RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
 // RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o

test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir

@@ -5,7 +5,7 @@
 // RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
 // RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/bf16xbf16_mul_elem/testbench.cc

@@ -5,17 +5,12 @@
 #include <cstdio>
 #include <cstdlib>
 
-#ifdef TO_CPP
+#ifdef TO_LLVM
+extern "C" {
+#endif
 void dut(bfloat16 *restrict in0, bfloat16 *restrict in1,
          bfloat16 *restrict out0);
-#elif TO_LLVM
-extern "C" {
-void dut(bfloat16 *in0_allocated, bfloat16 *in0_aligned, int64_t in0_offset,
-         int64_t in0_sizes_0, int64_t in0_strides_0, bfloat16 *in1_allocated,
-         bfloat16 *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
-         int64_t in1_strides_0, bfloat16 *out0_allocated,
-         bfloat16 *out0_aligned, int64_t out0_offset, int64_t out0_sizes_0,
-         int64_t out0_strides_0);
+#ifdef TO_LLVM
 }
 #endif
 
@@ -39,11 +34,7 @@ int main(int argc, char *argv[]) {
 
   chess_memory_fence();
   auto cyclesBegin = chess_cycle_count();
-#ifdef TO_CPP
   dut(g_in0, g_in1, g_out0);
-#elif TO_LLVM
-  dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
-#endif
   auto cyclesEnd = chess_cycle_count();
   chess_memory_fence();
 

test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir

@@ -5,7 +5,7 @@
 // RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
 // RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/testbench.cc

@@ -5,15 +5,11 @@
 #include <cstdio>
 #include <cstdlib>
 
-#ifdef TO_CPP
-void dut(bfloat16 *restrict in0, bfloat16 *restrict in1, float *restrict out0);
-#elif TO_LLVM
+#ifdef TO_LLVM
 extern "C" {
-void dut(bfloat16 *in0_allocated, bfloat16 *in0_aligned, int64_t in0_offset,
-         int64_t in0_sizes_0, int64_t in0_strides_0, bfloat16 *in1_allocated,
-         bfloat16 *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
-         int64_t in1_strides_0, float *out0_allocated, float *out0_aligned,
-         int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
+#endif
+void dut(bfloat16 *restrict in0, bfloat16 *restrict in1, float *restrict out0);
+#ifdef TO_LLVM
 }
 #endif
 
@@ -37,11 +33,7 @@ int main(int argc, char *argv[]) {
 
   chess_memory_fence();
   auto cyclesBegin = chess_cycle_count();
-#ifdef TO_CPP
   dut(g_in0, g_in1, g_out0);
-#elif TO_LLVM
-  dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
-#endif
   auto cyclesEnd = chess_cycle_count();
   chess_memory_fence();
 

test/unit_tests/aievec_tests/floatxfloat_mul_elem/floatxfloat_mul_elem.mlir

@@ -5,7 +5,7 @@
 // RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
 // RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/floatxfloat_mul_elem/testbench.cc

@@ -5,15 +5,11 @@
 #include <cstdio>
 #include <cstdlib>
 
-#ifdef TO_CPP
-void dut(float *restrict in0, float *restrict in1, float *restrict out0);
-#elif TO_LLVM
+#ifdef TO_LLVM
 extern "C" {
-void dut(float *in0_allocated, float *in0_aligned, int64_t in0_offset,
-         int64_t in0_sizes_0, int64_t in0_strides_0, float *in1_allocated,
-         float *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
-         int64_t in1_strides_0, float *out0_allocated, float *out0_aligned,
-         int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
+#endif
+void dut(float *restrict in0, float *restrict in1, float *restrict out0);
+#ifdef TO_LLVM
 }
 #endif
 
@@ -37,11 +33,7 @@ int main(int argc, char *argv[]) {
 
   chess_memory_fence();
   auto cyclesBegin = chess_cycle_count();
-#ifdef TO_CPP
   dut(g_in0, g_in1, g_out0);
-#elif TO_LLVM
-  dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
-#endif
   auto cyclesEnd = chess_cycle_count();
   chess_memory_fence();
 

test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce-llvm.mlir

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<i16>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi16>
+    %c0_i16 = arith.constant 0 : i16
+    %cst = arith.constant dense<-32768> : vector<32xi16>
+    %0 = affine.for %arg2 = 0 to 1024 step 32 iter_args(%arg3 = %cst) -> (vector<32xi16>) {
+      %2 = vector.transfer_read %arg0[%arg2], %c0_i16 : memref<1024xi16>, vector<32xi16>
+      %3 = arith.maxsi %arg3, %2 : vector<32xi16>
+      affine.yield %3 : vector<32xi16>
+    }
+    %1 = vector.reduction <maxsi>, %0 : vector<32xi16> into i16
+    affine.store %1, %arg1[] : memref<i16>
+    return
+  }
+}

test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir

@@ -1,7 +1,11 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
-// RUN: mkdir -p data
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc

@@ -6,7 +6,14 @@
 #include <cstdlib>
 #include <limits.h>
 
+#ifdef TO_LLVM
+extern "C" {
+#endif
 void dut(int16_t *restrict in0, int16_t *restrict out0);
+#ifdef TO_LLVM
+}
+#endif
+
 void dut_ref(int16_t *in0, int16_t *out0);
 
 alignas(32) int16_t g_in0[IN0_SIZE];

test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce-llvm.mlir

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<i16>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi16>
+    %c0_i16 = arith.constant 0 : i16
+    %cst = arith.constant dense<32767> : vector<32xi16>
+    %0 = affine.for %arg2 = 0 to 1024 step 32 iter_args(%arg3 = %cst) -> (vector<32xi16>) {
+      %2 = vector.transfer_read %arg0[%arg2], %c0_i16 : memref<1024xi16>, vector<32xi16>
+      %3 = arith.minsi %arg3, %2 : vector<32xi16>
+      affine.yield %3 : vector<32xi16>
+    }
+    %1 = vector.reduction <minsi>, %0 : vector<32xi16> into i16
+    affine.store %1, %arg1[] : memref<i16>
+    return
+  }
+}

test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir

@@ -1,7 +1,11 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
-// RUN: mkdir -p data
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc

@@ -6,7 +6,14 @@
 #include <cstdlib>
 #include <limits.h>
 
+#ifdef TO_LLVM
+extern "C" {
+#endif
 void dut(int16_t *restrict in0, int16_t *restrict out0);
+#ifdef TO_LLVM
+}
+#endif
+
 void dut_ref(int16_t *in0, int16_t *out0);
 
 alignas(32) int16_t g_in0[IN0_SIZE];

test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce-llvm.mlir

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi32>, %arg1: memref<i32>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi32>
+    %c0_i32 = arith.constant 0 : i32
+    %cst = arith.constant dense<-2147483648> : vector<16xi32>
+    %0 = affine.for %arg2 = 0 to 1024 step 16 iter_args(%arg3 = %cst) -> (vector<16xi32>) {
+      %2 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<1024xi32>, vector<16xi32>
+      %3 = arith.maxsi %arg3, %2 : vector<16xi32>
+      affine.yield %3 : vector<16xi32>
+    }
+    %1 = vector.reduction <maxsi>, %0 : vector<16xi32> into i32
+    affine.store %1, %arg1[] : memref<i32>
+    return
+  }
+}

test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir

@@ -1,7 +1,11 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
-// RUN: mkdir -p data
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/i32_max_reduce/testbench.cc

@@ -6,7 +6,14 @@
 #include <cstdlib>
 #include <limits.h>
 
+#ifdef TO_LLVM
+extern "C" {
+#endif
 void dut(int32_t *restrict in0, int32_t *restrict out0);
+#ifdef TO_LLVM
+}
+#endif
+
 void dut_ref(int32_t *in0, int32_t *out0);
 
 alignas(32) int32_t g_in0[IN0_SIZE];

test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce-llvm.mlir

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi32>, %arg1: memref<i32>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi32>
+    %c0_i32 = arith.constant 0 : i32
+    %cst = arith.constant dense<2147483647> : vector<16xi32>
+    %0 = affine.for %arg2 = 0 to 1024 step 16 iter_args(%arg3 = %cst) -> (vector<16xi32>) {
+      %2 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<1024xi32>, vector<16xi32>
+      %3 = arith.minsi %arg3, %2 : vector<16xi32>
+      affine.yield %3 : vector<16xi32>
+    }
+    %1 = vector.reduction <minsi>, %0 : vector<16xi32> into i32
+    affine.store %1, %arg1[] : memref<i32>
+    return
+  }
+}

test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir

@@ -1,7 +1,11 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// RUN: mkdir -p %t/data; cd %t
 // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
-// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
-// RUN: mkdir -p data
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
 // RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
 // CHECK: TEST PASSED

test/unit_tests/aievec_tests/i32_min_reduce/testbench.cc

@@ -6,7 +6,14 @@
 #include <cstdlib>
 #include <limits.h>
 
+#ifdef TO_LLVM
+extern "C" {
+#endif
 void dut(int32_t *restrict in0, int32_t *restrict out0);
+#ifdef TO_LLVM
+}
+#endif
+
 void dut_ref(int32_t *in0, int32_t *out0);
 
 alignas(32) int32_t g_in0[IN0_SIZE];