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@pvasireddy-amd
pvasireddy-amd committed Oct 23, 2024
1 parent 6e40239 commit 58686f5
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Showing 2 changed files with 33 additions and 28 deletions.
49 changes: 26 additions & 23 deletions lib/Dialect/AIEX/Transforms/AIEDMATasksToNPU.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,8 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
}

LogicalResult rewriteSingleBD(OpBuilder &builder, Block &block,
AIE::TileOp &tile, AIE::DMAChannelDir channelDir) {
AIE::TileOp &tile,
AIE::DMAChannelDir channelDir) {
AIE::DMABDOp bd_op = getBdForBlock(block);
const auto &target_model = AIE::getTargetModel(bd_op);
MemRefType buffer_type = bd_op.getBuffer().getType();
Expand All @@ -242,11 +243,13 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
bd_op.getDimensions();
llvm::SmallVector<int64_t, 4> sizes = llvm::SmallVector<int64_t, 4>(4, 0);
llvm::SmallVector<int64_t, 4> strides = llvm::SmallVector<int64_t, 4>(4, 0);
// Padding
// Padding
std::optional<llvm::ArrayRef<AIE::BDPadLayoutAttr>> padDims =
bd_op.getPadDimensions();
llvm::SmallVector<int64_t, 4> padBefore = llvm::SmallVector<int64_t, 4>(4, 0);
llvm::SmallVector<int64_t, 4> padAfter = llvm::SmallVector<int64_t, 4>(4, 0);
llvm::SmallVector<int64_t, 4> padBefore =
llvm::SmallVector<int64_t, 4>(4, 0);
llvm::SmallVector<int64_t, 4> padAfter =
llvm::SmallVector<int64_t, 4>(4, 0);
std::fill(padBefore.begin(), padBefore.end(), 0);
std::fill(padAfter.begin(), padAfter.end(), 0);

Expand All @@ -268,20 +271,21 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
input_strides[i] = (*dims)[j].getStride();
}

if(target_model.isMemTile(tile.getCol(), tile.getRow()) &&
channelDir == AIE::DMAChannelDir::MM2S){
if(padDims && (padDims->size() > dims->size()))
return bd_op->emitOpError() << "Mismatch number of dimensions between padding(s)"
<< " and wrap(s) and stride(s).";
if (target_model.isMemTile(tile.getCol(), tile.getRow()) &&
channelDir == AIE::DMAChannelDir::MM2S) {
if (padDims && (padDims->size() > dims->size()))
return bd_op->emitOpError()
<< "Mismatch number of dimensions between padding(s)"
<< " and wrap(s) and stride(s).";
else if (padDims)
for (size_t i = 0; i < padDims->size(); i++) {
int j = padDims->size() - i - 1;
padBefore[i] = (*padDims)[j].getConstPadBefore();
padAfter[i] = (*padDims)[j].getConstPadAfter();
}
}
else{
return bd_op->emitOpError() << "supports padding only for MM2S direction on MemTiles.";
} else {
return bd_op->emitOpError()
<< "supports padding only for MM2S direction on MemTiles.";
}
getHardwareStridesWraps(target_model, buffer_type, input_sizes,
input_strides, sizes, strides);
Expand Down Expand Up @@ -313,14 +317,13 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
"transfer length, as this is the BD repeat count.";
return failure();
}
}
else{
if(padDims && target_model.isMemTile(tile.getCol(), tile.getRow()) &&
channelDir == AIE::DMAChannelDir::MM2S){
return bd_op->emitOpError() << "Padding requires n-d data layouts expressed as"
<< "wrap(s) and stride(s).";
}
else if (padDims){
} else {
if (padDims && target_model.isMemTile(tile.getCol(), tile.getRow()) &&
channelDir == AIE::DMAChannelDir::MM2S) {
return bd_op->emitOpError()
<< "Padding requires n-d data layouts expressed as"
<< "wrap(s) and stride(s).";
} else if (padDims) {
return bd_op->emitOpError() << "Padding is supported only on MemTiles.";
}
}
Expand Down Expand Up @@ -349,8 +352,8 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
/* TODO: Locks */
/*lock_rel_val=*/0, /*lock_rel_id=*/0, /*lock_acq_enable=*/0,
/*lock_acq_val=*/0, /*lock_ackq_id=*/0, /*d0_zero_before=*/padBefore[0],
/*d1_zero_before=*/padBefore[1], /*d2_zero_before=*/padBefore[2],
/*d0_zero_after=*/padAfter[0], /*d1_zero_after=*/padAfter[1],
/*d1_zero_before=*/padBefore[1], /*d2_zero_before=*/padBefore[2],
/*d0_zero_after=*/padAfter[0], /*d1_zero_after=*/padAfter[1],
/*d2_zero_after=*/padAfter[2]);

return setAddressForSingleBD(builder, bd_op, tile);
Expand Down Expand Up @@ -426,7 +429,7 @@ struct AIEDMATasksToNPUPass : AIEDMATasksToNPUBase<AIEDMATasksToNPUPass> {
if (failed(hoistNextBdOpsIntoAttrs(op))) {
return failure();
}

auto channelDir = op.getDirection();

// Lower all BDs
Expand Down
12 changes: 7 additions & 5 deletions lib/Dialect/AIEX/Transforms/AIEDmaToNpu.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -482,17 +482,17 @@ struct DmaToNpuPattern : OpConversionPattern<NpuDmaMemcpyNdOp> {
if (!isMM2S)
issue_token = BoolAttr::get(ctx, true);

// TODO: Need to add a check to only allow zero padding on MM2S channel of MemTile
// As of now, run time MemTile DMA configuration is supported only from BD level, not at
// NpuDmaMemcpyNdOp.
// TODO: Need to add a check to only allow zero padding on MM2S channel of
// MemTile As of now, run time MemTile DMA configuration is supported only
// from BD level, not at NpuDmaMemcpyNdOp.

rewriter.create<NpuWriteBdOp>(
op->getLoc(), column, bd_id, buffer_length, buffer_offset,
enable_packet, out_of_order_id, packet_id, packet_type, d0_size,
d0_stride, d1_size, d1_stride, d2_stride, iteration_current,
iteration_size, iteration_stride, next_bd, row, use_next_bd, valid_bd,
lock_rel_val, lock_rel_id, lock_acq_enable, lock_acq_val, lock_acq_id,
d0_zero_before, d1_zero_before, d2_zero_before, d0_zero_after,
d0_zero_before, d1_zero_before, d2_zero_before, d0_zero_after,
d1_zero_after, d2_zero_after);

uint64_t addr = getBufferDescriptorAddressRegisterAddress(
Expand Down Expand Up @@ -616,7 +616,9 @@ struct WriteBdToBlockWritePattern : OpConversionPattern<NpuWriteBdOp> {
words[7] |= (op.getLockAcqVal() & 0xef) << 5;
words[7] |= op.getLockAcqId() & 0xf;

if(op.getD0ZeroBefore() || op.getD1ZeroBefore() || op.getD2ZeroBefore() || op.getD0ZeroAfter() || op.getD1ZeroAfter() || op.getD2ZeroAfter()){
if (op.getD0ZeroBefore() || op.getD1ZeroBefore() ||
op.getD2ZeroBefore() || op.getD0ZeroAfter() || op.getD1ZeroAfter() ||
op.getD2ZeroAfter()) {
op->emitError("Zero padding is only available on MemTile");
}
} else if (tm.isMemTile(op.getColumn(), op.getRow())) {
Expand Down

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