Skip to content

Commit

Permalink
[asplos] mlir examples makefile edits and capitalization fixes (#1417)
Browse files Browse the repository at this point in the history
  • Loading branch information
@efurst
efurst authored Apr 25, 2024
1 parent 1b44c27 commit 5c16451
Show file tree
Hide file tree
Showing 9 changed files with 70 additions and 60 deletions.
2 changes: 1 addition & 1 deletion programming_examples/mlir/MM_2x2/circuit_switched_version/Makefile
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
include ../../../tutorials/makefile-common
include ../../../../mlir_tutorials/makefile-common

.PHONY: all clean

Expand Down
2 changes: 1 addition & 1 deletion programming_examples/mlir/MM_2x2/objectFifo_circuit_switched_version/Makefile
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
include ../../../tutorials/makefile-common
include ../../../../mlir_tutorials/makefile-common

.PHONY: all clean

Expand Down
2 changes: 1 addition & 1 deletion programming_examples/mlir/MM_2x2/packet_switched_version/Makefile
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
include ../../../tutorials/makefile-common
include ../../../../mlir_tutorials/makefile-common

.PHONY: all clean

Expand Down
18 changes: 10 additions & 8 deletions programming_examples/mlir/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,32 +4,34 @@
# This file is licensed under the MIT License.
# SPDX-License-Identifier: MIT

include ../../../../mlir_tutorials/makefile-common

ACDC_AIE = $(dir $(shell which aie-opt))/..
ACDC_AIR = $(dir $(shell which air-opt))/..
SYSROOT = $XILINX_SYSROOT
SYSROOT = $(XILINX_SYSROOT)

i32: i32_chess i32.elf
f32: f32_chess f32.elf

build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl
xca_udm_dbg -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

f32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

clean:
rm -rf work *mem acdc_project core_* test.elf *.o
Expand Down
18 changes: 10 additions & 8 deletions programming_examples/mlir/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,11 @@
# This file is licensed under the MIT License.
# SPDX-License-Identifier: MIT

include ../../../../mlir_tutorials/makefile-common

ACDC_AIE = $(dir $(shell which aie-opt))/..
ACDC_AIR = $(dir $(shell which air-opt))/..
SYSROOT = $XILINX_SYSROOT
SYSROOT = $(XILINX_SYSROOT)

i32: i32_chess i32.elf
f32: f32_chess f32.elf
Expand All @@ -15,23 +17,23 @@ f32: f32_chess f32.elf
build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl
xca_udm_dbg -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c hdiff.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c hdiff_fp32.cc


i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

f32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf


clean:
Expand Down
18 changes: 10 additions & 8 deletions ...ramming_examples/mlir/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,33 +4,35 @@
# This file is licensed under the MIT License.
# SPDX-License-Identifier: MIT

include ../../../../mlir_tutorials/makefile-common

ACDC_AIE = $(dir $(shell which aie-opt))/..
ACDC_AIR = $(dir $(shell which air-opt))/..
SYSROOT = $XILINX_SYSROOT
SYSROOT = $(XILINX_SYSROOT)

i32: i32_chess i32.elf
f32: f32_chess f32.elf

build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl
xca_udm_dbg -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c hdiff.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c hdiff_fp32.cc


i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

f32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf


clean:
Expand Down
18 changes: 10 additions & 8 deletions programming_examples/mlir/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,33 +4,35 @@
# This file is licensed under the MIT License.
# SPDX-License-Identifier: MIT

include ../../../../mlir_tutorials/makefile-common

ACDC_AIE = $(dir $(shell which aie-opt))/..
ACDC_AIR = $(dir $(shell which air-opt))/..
SYSROOT = $XILINX_SYSROOT
SYSROOT = $(XILINX_SYSROOT)

i32: i32_chess i32.elf
f32: f32_chess f32.elf

build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl
xca_udm_dbg -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf


f32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

clean:
rm -rf work *mem acdc_project core_* test.elf *.o
Expand Down
18 changes: 10 additions & 8 deletions ...ing_examples/mlir/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,33 +4,35 @@
# This file is licensed under the MIT License.
# SPDX-License-Identifier: MIT

include ../../../../mlir_tutorials/makefile-common

ACDC_AIE = $(dir $(shell which aie-opt))/..
ACDC_AIR = $(dir $(shell which air-opt))/..
SYSROOT = $XILINX_SYSROOT
SYSROOT = $(XILINX_SYSROOT)

i32: i32_chess i32.elf
f32: f32_chess f32.elf

build:
xchessmk test.prx
sim:
xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl
xca_udm_dbg -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -t sim.tcl


i32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc

f32_chess:
xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc
xchesscc -p me -P $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -L $(VITIS_AIETOOLS_DIR)/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc

i32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_$(b).mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test_$(b).cpp -o test_$(b).elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_$(b).mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test_$(b).cpp -o test_$(b).elf


f32.elf:
aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$RUNTIME_LIB $RUNTIME_LIB/test_library.cpp ./test.cpp -o test.elf
aiecc.py --sysroot=$(SYSROOT) --host-target=aarch64-linux-gnu aie_fp32.mlir \
-I$(AIE_RUNTIME_LIB) $(AIE_RUNTIME_LIB)/test_library.cpp ./test.cpp -o test.elf

clean:
rm -rf work *mem acdc_project core_* test.elf *.o
Expand Down
34 changes: 17 additions & 17 deletions programming_examples/mlir/prime_sieve_large/code_gen.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,14 +78,14 @@ def main():

for col in range(startcol, startcol + arraycols): # col 0 is reserved in aie
for row in range(1, rows): # row 1 -> 8
f.write(" %%tile%d_%d = AIE.tile(%d, %d)\n" % (col, row, col, row))
f.write(" %%tile%d_%d = aie.tile(%d, %d)\n" % (col, row, col, row))

# %objFifo = AIE.objectfifo.createObjectFifo(%tile12, {%tile33}, 2) : !AIE.objectfifo<memref<16xi32>>
# %objFifo = aie.objectfifo.createObjectFifo(%tile12, {%tile33}, 2) : !aie.objectfifo<memref<16xi32>>

# %subview = AIE.objectfifo.acquire<Produce>(%objFifo : !AIE.objectfifo<memref<16xi32>>, 1) : !AIE.objectfifosubview<memref<16xi32>>
# %elem0 = AIE.objectfifo.subview.access %subview[0] : !AIE.objectfifosubview<memref<16xi32>> -> memref<16xi32>
# %subview = aie.objectfifo.acquire<Produce>(%objFifo : !aie.objectfifo<memref<16xi32>>, 1) : !aie.objectfifosubview<memref<16xi32>>
# %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview<memref<16xi32>> -> memref<16xi32>

# AIE.objectfifo.release<Produce>(%objFifo : !AIE.objectfifo<memref<16xi32>>, 1)
# aie.objectfifo.release<Produce>(%objFifo : !aie.objectfifo<memref<16xi32>>, 1)

f.write("\n")
col = startcol
Expand All @@ -98,7 +98,7 @@ def main():
lockrow = row
lockcol = col
f.write(
" %%lock%d_%d = AIE.lock(%%tile%d_%d)\n" % (col, row, lockcol, lockrow)
" %%lock%d_%d = aie.lock(%%tile%d_%d)\n" % (col, row, lockcol, lockrow)
)

col = col + 1
Expand All @@ -115,7 +115,7 @@ def main():
lockrow = row
lockcol = col
f.write(
" %%lock%d_%d = AIE.lock(%%tile%d_%d)%s\n"
" %%lock%d_%d = aie.lock(%%tile%d_%d)%s\n"
% (col, row, lockcol, lockrow, symbol)
)
col = col + 1
Expand Down Expand Up @@ -147,7 +147,7 @@ def gen_buffer(row, col, lastrow):
lockrow = row
lockcol = col
f.write(
' %%buf%d_%d = AIE.buffer(%%tile%d_%d) { sym_name = "%s" } : memref<%dxi32>\n'
' %%buf%d_%d = aie.buffer(%%tile%d_%d) { sym_name = "%s" } : memref<%dxi32>\n'
% (col, row, lockcol, lockrow, symbol, bufsize)
)

Expand All @@ -170,7 +170,7 @@ def gen_buffer(row, col, lastrow):
"""
%core"""
+ str(startcol)
+ """_1 = AIE.core(%tile"""
+ """_1 = aie.core(%tile"""
+ str(startcol)
+ """_1) {
%c0 = arith.constant 0 : index
Expand Down Expand Up @@ -199,10 +199,10 @@ def gen_buffer(row, col, lastrow):
+ """xi32>
scf.yield %sum_next : i32
}
AIE.useLock(%lock"""
aie.use_lock(%lock"""
+ str(startcol)
+ """_1, "Release", 1)
AIE.end
aie.end
}
func.func @do_sieve(%bufin: memref<"""
+ str(bufsize)
Expand Down Expand Up @@ -292,16 +292,16 @@ def gen_core(col, row, col_p, row_p):
if col == startcol and row == 1:
None
else:
f.write(" %%core%d_%d = AIE.core(%%tile%d_%d) {\n" % (col, row, col, row))
f.write(' AIE.useLock(%%lock%d_%d, "Acquire", 1)\n' % (col_p, row_p))
f.write(' AIE.useLock(%%lock%d_%d, "Acquire", 0)\n' % (col, row))
f.write(" %%core%d_%d = aie.core(%%tile%d_%d) {\n" % (col, row, col, row))
f.write(' aie.use_lock(%%lock%d_%d, "Acquire", 1)\n' % (col_p, row_p))
f.write(' aie.use_lock(%%lock%d_%d, "Acquire", 0)\n' % (col, row))
f.write(
" func.call @do_sieve(%%buf%d_%d, %%buf%d_%d) : (memref<%dxi32>, memref<%dxi32>) -> ()\n"
% (col_p, row_p, col, row, bufsize, bufsize)
)
f.write(' AIE.useLock(%%lock%d_%d, "Release", 0)\n' % (col_p, row_p))
f.write(' AIE.useLock(%%lock%d_%d, "Release", 1)\n' % (col, row))
f.write(" AIE.end\n")
f.write(' aie.use_lock(%%lock%d_%d, "Release", 0)\n' % (col_p, row_p))
f.write(' aie.use_lock(%%lock%d_%d, "Release", 1)\n' % (col, row))
f.write(" aie.end\n")
f.write(" }\n\n")

col = startcol
Expand Down

0 comments on commit 5c16451

Please sign in to comment.