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[aievec] add aievec.min/max e2e to-llvm tests (#1528)
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jamestcl-amd authored Jun 10, 2024
1 parent 1a362e6 commit 9716dc7
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Showing 21 changed files with 328 additions and 42 deletions.
10 changes: 6 additions & 4 deletions lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1584,9 +1584,10 @@ class MaxOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::MaxOp> {
// create xllvm intrinsic
Value maxOp = nullptr;
if (llvm::isa<IntegerType>(resultScaTy)) {
// create constant for cmp
// create constant for third operand `cmp`
// Note: `cmp` is implicitly treated as `sign` to the vmax intrinsic
auto cmpCst = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
SmallVector<Value> operands{adaptor.getLhs(), adaptor.getRhs(), cmpCst};
if (resultBitWidth == 8) {
maxOp = rewriter.create<xllvm::VectorMaxLt8IntrOp>(
Expand Down Expand Up @@ -1681,9 +1682,10 @@ class MinOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::MinOp> {
// create xllvm intrinsic
Value minOp = nullptr;
if (llvm::isa<IntegerType>(resultScaTy)) {
// create constant for cmp
// create constant for third operand `cmp`
// Note: `cmp` is implicitly treated as `sign` to the vmin intrinsic
auto cmpCst = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
SmallVector<Value> operands{adaptor.getLhs(), adaptor.getRhs(), cmpCst};
if (resultBitWidth == 8) {
minOp = rewriter.create<xllvm::VectorMinGe8IntrOp>(
Expand Down
6 changes: 3 additions & 3 deletions test/Conversion/AIEVecToLLVM/test-max.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ func.func @i8_max(%arg0 : vector<64xi8>) -> vector<64xi8> {

// CHECK-LABEL: @i8_max
// CHECK-SAME: %[[ARG0:.*]]: vector<64xi8>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMAX:.*]] = "xllvm.intr.aie2.vmax.lt8"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, vector<2xi32>)>
Expand All @@ -23,7 +23,7 @@ func.func @i16_max(%arg0 : vector<32xi16>) -> vector<32xi16> {

// CHECK-LABEL: @i16_max
// CHECK-SAME: %[[ARG0:.*]]: vector<32xi16>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMAX:.*]] = "xllvm.intr.aie2.vmax.lt16"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<32xi16>, vector<32xi16>, i32) -> !llvm.struct<(vector<32xi16>, i32)>
Expand All @@ -39,7 +39,7 @@ func.func @i32_max(%arg0 : vector<16xi32>) -> vector<16xi32> {

// CHECK-LABEL: @i32_max
// CHECK-SAME: %[[ARG0:.*]]: vector<16xi32>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMAX:.*]] = "xllvm.intr.aie2.vmax.lt32"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32) -> !llvm.struct<(vector<16xi32>, i32)>
Expand Down
6 changes: 3 additions & 3 deletions test/Conversion/AIEVecToLLVM/test-min.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ func.func @i8_min(%arg0 : vector<64xi8>) -> vector<64xi8> {

// CHECK-LABEL: @i8_min
// CHECK-SAME: %[[ARG0:.*]]: vector<64xi8>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge8"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, vector<2xi32>)>
Expand All @@ -23,7 +23,7 @@ func.func @i16_min(%arg0 : vector<32xi16>) -> vector<32xi16> {

// CHECK-LABEL: @i16_min
// CHECK-SAME: %[[ARG0:.*]]: vector<32xi16>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge16"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<32xi16>, vector<32xi16>, i32) -> !llvm.struct<(vector<32xi16>, i32)>
Expand All @@ -39,7 +39,7 @@ func.func @i32_min(%arg0 : vector<16xi32>) -> vector<16xi32> {

// CHECK-LABEL: @i32_min
// CHECK-SAME: %[[ARG0:.*]]: vector<16xi32>
// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[CST:.*]] = llvm.mlir.constant(1 : i32) : i32
// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge32"(
// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) :
// CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32) -> !llvm.struct<(vector<16xi32>, i32)>
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// REQUIRES: peano
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" %vector-to-llvmir% -o llvmir.mlir
// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED

module {
func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<1024xi16>, %arg2: memref<1024xi16>) {
memref.assume_alignment %arg0, 32 : memref<1024xi16>
memref.assume_alignment %arg1, 32 : memref<1024xi16>
memref.assume_alignment %arg2, 32 : memref<1024xi16>
affine.for %arg3 = 0 to 1024 {
%0 = affine.load %arg0[%arg3] : memref<1024xi16>
%1 = affine.load %arg1[%arg3] : memref<1024xi16>
%2 = arith.maxsi %0, %1 : i16
affine.store %2, %arg2[%arg3] : memref<1024xi16>
}
return
}
}
Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: mkdir -p data
// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED
Expand Down
16 changes: 16 additions & 0 deletions test/unit_tests/aievec_tests/i16xi16_max_elem/testbench.cc
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,19 @@
#include <cstdint>
#include <cstdio>
#include <cstdlib>

#ifdef TO_CPP
void dut(int16_t *restrict in0, int16_t *restrict in1, int16_t *restrict out0);
#elif TO_LLVM
extern "C" {
void dut(int16_t *in0_allocated, int16_t *in0_aligned, int64_t in0_offset,
int64_t in0_sizes_0, int64_t in0_strides_0, int16_t *in1_allocated,
int16_t *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
int64_t in1_strides_0, int16_t *out0_allocated, int16_t *out0_aligned,
int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
}
#endif

void dut_ref(int16_t *in0, int16_t *in1, int16_t *out0);

alignas(32) int16_t g_in0[IN0_SIZE];
Expand All @@ -26,7 +38,11 @@ int main(int argc, char *argv[]) {

chess_memory_fence();
auto cyclesBegin = chess_cycle_count();
#ifdef TO_CPP
dut(g_in0, g_in1, g_out0);
#elif TO_LLVM
dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
#endif
auto cyclesEnd = chess_cycle_count();
chess_memory_fence();

Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// REQUIRES: peano
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" %vector-to-llvmir% -o llvmir.mlir
// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED

module {
func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<1024xi16>, %arg2: memref<1024xi16>) {
memref.assume_alignment %arg0, 32 : memref<1024xi16>
memref.assume_alignment %arg1, 32 : memref<1024xi16>
memref.assume_alignment %arg2, 32 : memref<1024xi16>
affine.for %arg3 = 0 to 1024 {
%0 = affine.load %arg0[%arg3] : memref<1024xi16>
%1 = affine.load %arg1[%arg3] : memref<1024xi16>
%2 = arith.minsi %0, %1 : i16
affine.store %2, %arg2[%arg3] : memref<1024xi16>
}
return
}
}
Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: mkdir -p data
// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED
Expand Down
14 changes: 14 additions & 0 deletions test/unit_tests/aievec_tests/i16xi16_min_elem/testbench.cc
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,17 @@
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#ifdef TO_CPP
void dut(int16_t *restrict in0, int16_t *restrict in1, int16_t *restrict out0);
#elif TO_LLVM
extern "C" {
void dut(int16_t *in0_allocated, int16_t *in0_aligned, int64_t in0_offset,
int64_t in0_sizes_0, int64_t in0_strides_0, int16_t *in1_allocated,
int16_t *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
int64_t in1_strides_0, int16_t *out0_allocated, int16_t *out0_aligned,
int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
}
#endif
void dut_ref(int16_t *in0, int16_t *in1, int16_t *out0);

alignas(32) int16_t g_in0[IN0_SIZE];
Expand All @@ -26,7 +36,11 @@ int main(int argc, char *argv[]) {

chess_memory_fence();
auto cyclesBegin = chess_cycle_count();
#ifdef TO_CPP
dut(g_in0, g_in1, g_out0);
#elif TO_LLVM
dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
#endif
auto cyclesEnd = chess_cycle_count();
chess_memory_fence();

Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// REQUIRES: peano
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" %vector-to-llvmir% -o llvmir.mlir
// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED

module {
func.func @dut(%arg0: memref<1024xi32>, %arg1: memref<1024xi32>, %arg2: memref<1024xi32>) {
memref.assume_alignment %arg0, 32 : memref<1024xi32>
memref.assume_alignment %arg1, 32 : memref<1024xi32>
memref.assume_alignment %arg2, 32 : memref<1024xi32>
affine.for %arg3 = 0 to 1024 {
%0 = affine.load %arg0[%arg3] : memref<1024xi32>
%1 = affine.load %arg1[%arg3] : memref<1024xi32>
%2 = arith.maxsi %0, %1 : i32
affine.store %2, %arg2[%arg3] : memref<1024xi32>
}
return
}
}
Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: mkdir -p data
// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED
Expand Down
16 changes: 16 additions & 0 deletions test/unit_tests/aievec_tests/i32xi32_max_elem/testbench.cc
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,19 @@
#include <cstdint>
#include <cstdio>
#include <cstdlib>

#ifdef TO_CPP
void dut(int32_t *restrict in0, int32_t *restrict in1, int32_t *restrict out0);
#elif TO_LLVM
extern "C" {
void dut(int32_t *in0_allocated, int32_t *in0_aligned, int64_t in0_offset,
int64_t in0_sizes_0, int64_t in0_strides_0, int32_t *in1_allocated,
int32_t *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
int64_t in1_strides_0, int32_t *out0_allocated, int32_t *out0_aligned,
int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
}
#endif

void dut_ref(int32_t *in0, int32_t *in1, int32_t *out0);

alignas(32) int32_t g_in0[IN0_SIZE];
Expand All @@ -26,7 +38,11 @@ int main(int argc, char *argv[]) {

chess_memory_fence();
auto cyclesBegin = chess_cycle_count();
#ifdef TO_CPP
dut(g_in0, g_in1, g_out0);
#elif TO_LLVM
dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
#endif
auto cyclesEnd = chess_cycle_count();
chess_memory_fence();

Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// REQUIRES: peano
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" %vector-to-llvmir% -o llvmir.mlir
// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED

module {
func.func @dut(%arg0: memref<1024xi32>, %arg1: memref<1024xi32>, %arg2: memref<1024xi32>) {
memref.assume_alignment %arg0, 32 : memref<1024xi32>
memref.assume_alignment %arg1, 32 : memref<1024xi32>
memref.assume_alignment %arg2, 32 : memref<1024xi32>
affine.for %arg3 = 0 to 1024 {
%0 = affine.load %arg0[%arg3] : memref<1024xi32>
%1 = affine.load %arg1[%arg3] : memref<1024xi32>
%2 = arith.minsi %0, %1 : i32
affine.store %2, %arg2[%arg3] : memref<1024xi32>
}
return
}
}
Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

// REQUIRES: valid_xchess_license
// RUN: mkdir -p %t/data; cd %t
// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: mkdir -p data
// RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
// CHECK: TEST PASSED
Expand Down
16 changes: 16 additions & 0 deletions test/unit_tests/aievec_tests/i32xi32_min_elem/testbench.cc
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,19 @@
#include <cstdint>
#include <cstdio>
#include <cstdlib>

#ifdef TO_CPP
void dut(int32_t *restrict in0, int32_t *restrict in1, int32_t *restrict out0);
#elif TO_LLVM
extern "C" {
void dut(int32_t *in0_allocated, int32_t *in0_aligned, int64_t in0_offset,
int64_t in0_sizes_0, int64_t in0_strides_0, int32_t *in1_allocated,
int32_t *in1_aligned, int64_t in1_offset, int64_t in1_sizes_0,
int64_t in1_strides_0, int32_t *out0_allocated, int32_t *out0_aligned,
int64_t out0_offset, int64_t out0_sizes_0, int64_t out0_strides_0);
}
#endif

void dut_ref(int32_t *in0, int32_t *in1, int32_t *out0);

alignas(32) int32_t g_in0[IN0_SIZE];
Expand All @@ -26,7 +38,11 @@ int main(int argc, char *argv[]) {

chess_memory_fence();
auto cyclesBegin = chess_cycle_count();
#ifdef TO_CPP
dut(g_in0, g_in1, g_out0);
#elif TO_LLVM
dut(g_in0, g_in0, 0, 0, 0, g_in1, g_in1, 0, 0, 0, g_out0, g_out0, 0, 0, 0);
#endif
auto cyclesEnd = chess_cycle_count();
chess_memory_fence();

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