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[aievec] Add lowering for vector.extract_strided_slice
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This is part of the canonical lowering of unaligned transfer read ops.

For now we only support extracting a contiguous vector of half the size
of the source vector.
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jsetoain committed Aug 10, 2023
1 parent 1cf0528 commit 9ccfcdd
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Showing 32 changed files with 1,849 additions and 730 deletions.
12 changes: 12 additions & 0 deletions include/aie/Dialect/AIEVec/Analysis/CMakeLists.txt
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#
# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2022 Xilinx Inc.

set(LLVM_TARGET_DEFINITIONS Passes.td)
mlir_tablegen(Passes.h.inc -gen-pass-decls -name AIEVecAnalysis)
add_public_tablegen_target(MLIRAIEVecAnalysisPassIncGen)

add_mlir_doc(Passes AIEVecAnalysisPasses ./ -gen-pass-doc)
46 changes: 46 additions & 0 deletions include/aie/Dialect/AIEVec/Analysis/Passes.h
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//===- Passes.h - AIE Vector Passes -----------------------------*- C++ -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2022 Xilinx Inc.
//
//===----------------------------------------------------------------------===//
// Register all the AIE vectorization passes
//===----------------------------------------------------------------------===//

#ifndef AIE_DIALECT_AIEVEC_ANALYSIS_PASSES_H
#define AIE_DIALECT_AIEVEC_ANALYSIS_PASSES_H

#include "mlir/Pass/Pass.h"
#include "mlir/Pass/PassOptions.h"
#include <limits>

//===----------------------------------------------------------------------===//
// Registration
//===----------------------------------------------------------------------===//

namespace mlir {
namespace func {
class FuncOp;
} // namespace func
} // namespace mlir

namespace xilinx {
namespace aievec {

#define GEN_PASS_DECL
#define GEN_PASS_CLASSES
#include "aie/Dialect/AIEVec/Analysis/Passes.h.inc"

std::unique_ptr<Pass> createAIEVecConvolutionAnalysisPass();

/// Generate the code for registering passes.
#define GEN_PASS_REGISTRATION
#include "aie/Dialect/AIEVec/Analysis/Passes.h.inc"

} // end namespace aievec
} // end namespace xilinx

#endif // AIE_DIALECT_AIEVEC_ANALYSIS_PASSES_H
28 changes: 28 additions & 0 deletions include/aie/Dialect/AIEVec/Analysis/Passes.td
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//=== Passes.td - AIE vector analysis pass definition file -*- tablegen -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023 AMD Inc.
//
//===----------------------------------------------------------------------===//
// This file contains definitions for passes within the AIEVec/ directory.
//===----------------------------------------------------------------------===//

#ifndef AIE_DIALECT_AIEVEC_ANALYSIS_PASSES
#define AIE_DIALECT_AIEVEC_ANALYSIS_PASSES

include "mlir/Pass/PassBase.td"

def AIEVecConvAnalysis : Pass<"aievec-convolution-analysis", "mlir::func::FuncOp"> {
let summary = "Find MAC chains that can be replaced by convolution ops in "
"AIE-ML";
let constructor = "xilinx::aievec::createAIEVecConvolutionAnalysisPass()";
let options = [
Option<"printResult", "print", "bool", /*default=*/"false",
"Print the result of the analysis">,
];
}

#endif // AIE_DIALECT_AIEVEC_ANALYSIS_PASSES
1 change: 1 addition & 0 deletions include/aie/Dialect/AIEVec/CMakeLists.txt
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Expand Up @@ -5,5 +5,6 @@
#
# (c) Copyright 2022 Xilinx Inc.

add_subdirectory(Analysis)
add_subdirectory(IR)
add_subdirectory(Transforms)
14 changes: 9 additions & 5 deletions lib/Dialect/AIEVec/Transforms/AIEVecOptimizations.cpp
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@@ -1,4 +1,5 @@
#include "aie/Dialect/AIEVec/AIEVecUtils.h"
#include "aie/Dialect/AIEVec/Analysis/Passes.h"
#include "aie/Dialect/AIEVec/IR/AIEVecOps.h"
#include "mlir/Dialect/Affine/IR/AffineOps.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
Expand Down Expand Up @@ -192,6 +193,10 @@ populateAIEVecV2TransformationPatterns(RewritePatternSet &patterns) {
patterns.add<FoldAIEShiftAndBroadcast>(patterns.getContext());
}

//===----------------------------------------------------------------------===//
// Legalizations
//===----------------------------------------------------------------------===//

static void
configureAIEVecV1TransformationLegalizations(ConversionTarget &target) {
target.addLegalDialect<aievec::AIEVecDialect>();
Expand All @@ -202,9 +207,6 @@ configureAIEVecV1TransformationLegalizations(ConversionTarget &target) {
});
}

//===----------------------------------------------------------------------===//
// Legalizations
//===----------------------------------------------------------------------===//
static void
configureAIEVecV2TransformationLegalizations(ConversionTarget &target) {
target.addDynamicallyLegalOp<xilinx::aievec::BroadcastOp>(
Expand Down Expand Up @@ -373,9 +375,11 @@ void xilinx::aievec::buildOptimizeAIEVec(OpPassManager &pm,
pm.addPass(createCSEPass());
pm.addPass(createCanonicalizerPass());

// TODO: This pass should only be included if the target is AIEML.
// Add generating aievec convolution ops pass
pm.addPass(createAIEVecConvOpTransformationPass(options));
if (options.aieTarget == "aieml") {
pm.addPass(createAIEVecConvolutionAnalysisPass());
pm.addPass(createAIEVecConvOpTransformationPass(options));
}

// Add post-lowering canonicalization passes.
pm.addPass(createCSEPass());
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2 changes: 2 additions & 0 deletions lib/Dialect/AIEVec/Transforms/CMakeLists.txt
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Expand Up @@ -16,9 +16,11 @@ add_mlir_dialect_library(MLIRAIEVecTransforms

ADDITIONAL_HEADER_DIRS
${CMAKE_CURRENT_SOURCE_DIR}/../../../include/aie/Dialect/AIEVec/Transforms
${CMAKE_CURRENT_SOURCE_DIR}/../../../include/aie/Dialect/AIEVec/Analysis

DEPENDS
MLIRAIEVecPassIncGen
MLIRAIEVecAnalysisPassIncGen

LINK_LIBS PUBLIC
MLIRIR
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10 changes: 8 additions & 2 deletions lib/Dialect/AIEVec/Transforms/ConvertVectorToAIEVec.cpp
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Expand Up @@ -45,6 +45,10 @@ using namespace xilinx::aievec;

#define DEBUG_TYPE "vector-to-aievec-conversion"

//===----------------------------------------------------------------------===//
// Rewrite patterns
//===----------------------------------------------------------------------===//

template <typename OpTy>
struct SetInboundsToReadStoreOpPattern : public RewritePattern {
SetInboundsToReadStoreOpPattern(MLIRContext *context)
Expand Down Expand Up @@ -73,6 +77,10 @@ struct SetInboundsToReadStoreOpPattern : public RewritePattern {
using SetInboundsToReadOp = SetInboundsToReadStoreOpPattern<TransferReadOp>;
using SetInboundsToWriteOp = SetInboundsToReadStoreOpPattern<TransferWriteOp>;

//===----------------------------------------------------------------------===//
// Lowering passes
//===----------------------------------------------------------------------===//

struct RedundantLoadStoreOptimizationPass
: public PassWrapper<RedundantLoadStoreOptimizationPass,
OperationPass<func::FuncOp>> {
Expand Down Expand Up @@ -111,7 +119,6 @@ void xilinx::aievec::buildConvertVectorToAIEVec(
// NOTE: This sub-pipeline ingests arbitrary MLIR Vector code.
buildCanonicalizeVectorForAIEVec(
pm, options.getCanonicalizeVectorForAIEVecOptions());

// NOTE: At this stage, all the Vector code in the IR can be mapped
// HOTE: to AIEVec operations.

Expand All @@ -122,7 +129,6 @@ void xilinx::aievec::buildConvertVectorToAIEVec(
// NOTE: This sub-pipeline ingests MLIR Vector code that can be mapped to
// NOTE: AIEVec operations.
buildLowerVectorToAIEVec(pm, options.getLowerVectorToAIEVecOptions());

// NOTE: At this stage, all vector operations are expressed in AIEVec dialect.

//============================================================================
Expand Down
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