Merge branch 'main' into peano

Xilinx · Jun 11, 2024 · b92ef81 · b92ef81
2 parents 2d00899 + 0504f7a
commit b92ef81
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Showing 122 changed files with 1,546 additions and 1,179 deletions.
diff --git a/include/aie-c/TargetModel.h b/include/aie-c/TargetModel.h
@@ -42,6 +42,10 @@ DEFINE_C_API_STRUCT(AieTargetModel, uint64_t);
 
 MLIR_CAPI_EXPORTED AieTargetModel aieGetTargetModel(uint32_t device);
 
+/// Returns the data bus width for the target model.
+MLIR_CAPI_EXPORTED uint32_t
+aieGetTargetModelAddressGenGranularity(AieTargetModel targetModel);
+
 /// Returns the number of columns in the target model.
 MLIR_CAPI_EXPORTED int aieTargetModelColumns(AieTargetModel targetModel);
 

diff --git a/include/aie/Dialect/AIE/IR/AIETargetModel.h b/include/aie/Dialect/AIE/IR/AIETargetModel.h
@@ -61,6 +61,9 @@ class AIETargetModel {
   /// Return the target architecture.
   virtual AIEArch getTargetArch() const = 0;
 
+  /// Return the data bus width of the device.
+  virtual uint32_t getAddressGenGranularity() const = 0;
+
   /// Return the number of columns in the device.
   virtual int columns() const = 0;
 
@@ -293,6 +296,8 @@ class AIE2TargetModel : public AIETargetModel {
 
   AIEArch getTargetArch() const override;
 
+  uint32_t getAddressGenGranularity() const override { return 32; }
+
   std::optional<TileID> getMemWest(TileID src) const override;
   std::optional<TileID> getMemEast(TileID src) const override;
   std::optional<TileID> getMemNorth(TileID src) const override;
@@ -352,6 +357,8 @@ class VC1902TargetModel : public AIE1TargetModel {
 public:
   VC1902TargetModel() = default;
 
+  uint32_t getAddressGenGranularity() const override { return 32; }
+
   int columns() const override { return 50; }
 
   int rows() const override { return 9; /* One Shim row and 8 Core rows. */ }
@@ -532,6 +539,8 @@ class VirtualizedNPUTargetModel : public BaseNPUTargetModel {
 public:
   VirtualizedNPUTargetModel(int _cols) : cols(_cols) {}
 
+  uint32_t getAddressGenGranularity() const override { return 32; }
+
   int columns() const override { return cols; }
 
   bool isShimNOCTile(int col, int row) const override { return row == 0; }

diff --git a/include/aie/Dialect/AIEX/IR/AIEX.td b/include/aie/Dialect/AIEX/IR/AIEX.td
@@ -567,17 +567,20 @@ def AIE_NpuWriteRTPOp: AIEX_Op<"npu.rtp_write", []> {
 }
 
 // Push BD to Queue
-def AIE_NpuShimTilePushQueueOp: AIEX_Op<"npu.shimtile_push_queue", []> {
+def AIE_NpuPushQueueOp: AIEX_Op<"npu.push_queue", []> {
   let summary = "bd queue push operator";
   let arguments = (
-    ins FlatSymbolRefAttr:$metadata,
+    ins I32Attr:$column,
+        I32Attr:$row,
+        DMAChannelDir:$direction,
+        I32Attr:$channel,
         BoolAttr:$issue_token,
         I32Attr:$repeat_count,
         I32Attr:$bd_id
   );
   let results = (outs );
   let assemblyFormat = [{
-    attr-dict
+    `(` $column `,` $row `,` $direction `:` $channel `)` attr-dict
   }];
   let hasVerifier = 1;
   let description = [{
@@ -589,10 +592,10 @@ def AIE_NpuShimTilePushQueueOp: AIEX_Op<"npu.shimtile_push_queue", []> {
 def AIE_NpuWrite32Op: AIEX_Op<"npu.write32", []> {
   let summary = "write32 operator";
   let arguments = (
-    ins I32Attr:$column,
-        I32Attr:$row,
-        UI32Attr:$address,
-        UI32Attr:$value
+    ins UI32Attr:$address,
+        UI32Attr:$value,
+        OptionalAttr<I32Attr>:$column,
+        OptionalAttr<I32Attr>:$row
   );
   let results = (outs );
   let assemblyFormat = [{
@@ -623,12 +626,28 @@ def AIE_NpuSyncOp: AIEX_Op<"npu.sync", []> {
   }];
 }
 
-// WRITEBD_EXTEND_SHIMTILE
-def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"npu.writebd_shimtile", []> {
+// XAIE_IO_CUSTOM_OP_BEGIN + 1 (address patch)
+def AIE_NpuAddressPatchOp: AIEX_Op<"npu.address_patch", []> {
+  let summary = "address patch operator";
+  let arguments = (
+    ins UI32Attr:$addr,
+        I32Attr:$arg_idx,
+        I32Attr:$arg_plus
+  );
+  let results = (outs );
+  let assemblyFormat = [{
+    attr-dict
+  }];
+  let description = [{
+    address patch operator
+  }];
+}
+
+// NPU Bd Write operation
+def AIE_NpuWriteBdOp: AIEX_Op<"npu.writebd", []> {
   let summary = "dma operator";
   let arguments = (
     ins I32Attr:$column,
-        I32Attr:$column_num,
         I32Attr:$ddr_id,
         I32Attr:$bd_id,
         I32Attr:$buffer_length,
@@ -646,6 +665,7 @@ def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"npu.writebd_shimtile", []> {
         I32Attr:$iteration_size,
         I32Attr:$iteration_stride,
         I32Attr:$next_bd,
+        I32Attr:$row,
         I32Attr:$use_next_bd,
         I32Attr:$valid_bd,
         I32Attr:$lock_rel_val,
@@ -658,7 +678,7 @@ def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"npu.writebd_shimtile", []> {
   let assemblyFormat = [{ attr-dict }];
   let hasVerifier = 1;
   let description = [{
-    writebd_shimtile operator
+    writebd operator
   }];
 }
 

diff --git a/lib/CAPI/TargetModel.cpp b/lib/CAPI/TargetModel.cpp
@@ -28,6 +28,10 @@ AieTargetModel aieGetTargetModel(uint32_t device) {
       xilinx::AIE::getTargetModel(static_cast<xilinx::AIE::AIEDevice>(device)));
 }
 
+uint32_t aieGetTargetModelAddressGenGranularity(AieTargetModel targetModel) {
+  return unwrap(targetModel).getAddressGenGranularity();
+}
+
 int aieTargetModelColumns(AieTargetModel targetModel) {
   return unwrap(targetModel).columns();
 }

diff --git a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp
@@ -1584,9 +1584,10 @@ class MaxOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::MaxOp> {
     // create xllvm intrinsic
     Value maxOp = nullptr;
     if (llvm::isa<IntegerType>(resultScaTy)) {
-      // create constant for cmp
+      // create constant for third operand `cmp`
+      // Note: `cmp` is implicitly treated as `sign` to the vmax intrinsic
       auto cmpCst = rewriter.create<LLVM::ConstantOp>(
-          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
+          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
       SmallVector<Value> operands{adaptor.getLhs(), adaptor.getRhs(), cmpCst};
       if (resultBitWidth == 8) {
         maxOp = rewriter.create<xllvm::VectorMaxLt8IntrOp>(
@@ -1681,9 +1682,10 @@ class MinOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::MinOp> {
     // create xllvm intrinsic
     Value minOp = nullptr;
     if (llvm::isa<IntegerType>(resultScaTy)) {
-      // create constant for cmp
+      // create constant for third operand `cmp`
+      // Note: `cmp` is implicitly treated as `sign` to the vmin intrinsic
       auto cmpCst = rewriter.create<LLVM::ConstantOp>(
-          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
+          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
       SmallVector<Value> operands{adaptor.getLhs(), adaptor.getRhs(), cmpCst};
       if (resultBitWidth == 8) {
         minOp = rewriter.create<xllvm::VectorMinGe8IntrOp>(