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Update programming examples from tutorial branch (#1217)
Co-authored-by: Philip James-Roxby <phil.jamesroxby@gmail.com> Co-authored-by: pjr <pjr@xilinx.com> Co-authored-by: Joseph Melber <jgmelber@gmail.com>
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# This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
# (c) Copyright 2023 Advanced Micro Devices, Inc. | ||
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# parameters | ||
# -DBOOST_ROOT: Path to Boost install | ||
# -DXRT_INC_DIR: Full path to src/runtime_src/core/include in XRT cloned repo | ||
# -DXRT_LIB_DIR: Path to xrt_coreutil.lib | ||
# -DTARGET_NAME: Target name to be built | ||
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# cmake needs this line | ||
cmake_minimum_required(VERSION 3.1) | ||
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find_program(WSL NAMES powershell.exe) | ||
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if (NOT WSL) | ||
set(BOOST_ROOT /usr/include/boost CACHE STRING "Path to Boost install") | ||
set(XRT_INC_DIR /opt/xilinx/xrt/include CACHE STRING "Path to XRT cloned repo") | ||
set(XRT_LIB_DIR /opt/xilinx/xrt/lib CACHE STRING "Path to xrt_coreutil.lib") | ||
else() | ||
set(BOOST_ROOT C:/Technical/thirdParty/boost_1_83_0 CACHE STRING "Path to Boost install") | ||
set(XRT_INC_DIR C:/Technical/XRT/src/runtime_src/core/include CACHE STRING "Path to XRT cloned repo") | ||
set(XRT_LIB_DIR C:/Technical/xrtIPUfromDLL CACHE STRING "Path to xrt_coreutil.lib") | ||
endif() | ||
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set(TARGET_NAME test CACHE STRING "Target to be built") | ||
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SET (ProjectName ${TARGET_NAME}) | ||
SET (currentTarget ${TARGET_NAME}) | ||
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if ( WSL ) | ||
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY_RELEASE ${CMAKE_BINARY_DIR}) | ||
endif () | ||
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project(${ProjectName}) | ||
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# Find packages | ||
find_package(Boost REQUIRED) | ||
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add_executable(${currentTarget} | ||
test.cpp | ||
) | ||
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target_compile_definitions(${currentTarget} PUBLIC DISABLE_ABI_CHECK=1) | ||
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target_include_directories (${currentTarget} PUBLIC | ||
${XRT_INC_DIR} | ||
${Boost_INCLUDE_DIRS} | ||
../../../programming_examples/utils | ||
) | ||
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target_link_directories(${currentTarget} PUBLIC | ||
${XRT_LIB_DIR} | ||
${Boost_LIBRARY_DIRS} | ||
) | ||
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if (NOT WSL) | ||
target_link_libraries(${currentTarget} PUBLIC | ||
xrt_coreutil | ||
boost_program_options | ||
boost_filesystem | ||
) | ||
else() | ||
target_link_libraries(${currentTarget} PUBLIC | ||
xrt_coreutil | ||
) | ||
endif() |
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##===- Makefile -----------------------------------------------------------===## | ||
# | ||
# This file licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
##===----------------------------------------------------------------------===## | ||
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include ../../../programming_examples/basic/makefile-common | ||
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all: build/final.xclbin | ||
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targetname = myEltwiseMul | ||
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build/mul.o: | ||
mkdir -p ${@D} | ||
cd ${@D} && xchesscc_wrapper ${CHESSCCWRAP2_FLAGS} -I. -c ${REPO_ROOT}/aie_kernels/aie2/mul.cc -o ${@F} | ||
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build/aie.mlir: aie2.py | ||
mkdir -p ${@D} | ||
python3 $< > $@ | ||
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build/final.xclbin: build/aie.mlir build/mul.o | ||
mkdir -p ${@D} | ||
cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host \ | ||
--xclbin-name=${@F} --ipu-insts-name=insts.txt ${<F} | ||
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${targetname}.exe: test.cpp | ||
rm -rf _build | ||
mkdir -p _build | ||
# cd _build && ${powershell} cmake .. -DTARGET_NAME=${targetname} | ||
cd _build && ${powershell} cmake -E env CXXFLAGS="-std=c++23 -ggdb" cmake .. -D CMAKE_C_COMPILER=gcc-13 -D CMAKE_CXX_COMPILER=g++-13 -DTARGET_NAME=${targetname} -Dsubdir=${subdir} | ||
cd _build && ${powershell} cmake --build . --config Release | ||
ifeq "${powershell}" "powershell.exe" | ||
cp _build/${targetname}.exe $@ | ||
else | ||
cp _build/${targetname} $@ | ||
endif | ||
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run: ${targetname}.exe build/final.xclbin build/insts.txt | ||
${powershell} ./$< -x build/final.xclbin -i build/insts.txt -k MLIR_AIE | ||
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run_py: build/final.xclbin build/insts.txt | ||
${powershell} python3 test.py -x build/final.xclbin -i build/insts.txt -k MLIR_AIE | ||
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clean: | ||
rm -rf build _build ${targetname}.exe |
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<!---//===- README.md --------------------------*- Markdown -*-===// | ||
// | ||
// This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
// Copyright (C) 2022, Advanced Micro Devices, Inc. | ||
// | ||
//===----------------------------------------------------------------------===//--> | ||
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# <ins>Section 3 - My First Program</ins> | ||
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In this section, we'll put together what you learend in [section-1](../section-1) for defining a basic strucutral design in python and combine it with the data movement part from [section-2](../section-2) to build our first program. We will then run a simulation on this program as well as run this design on hardware (Ryzen AI). | ||
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* Introduce example of first simple program (Bias Add) | ||
* Walk through syntax of aie2.py, test.cpp, test_utils.h, maybe CMakeLists.txt and Makefile/ makefile-common as well | ||
* need to remove trace parts from test.cpp for now and move it to Section-4 | ||
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* Illustrate how built-in simulation of single core design | ||
* Illustrate how to run designs on Ryzen AI enabled hardware |
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# | ||
# This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
# (c) Copyright 2023 AMD Inc. | ||
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import sys | ||
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from aie.dialects.aie import * | ||
from aie.dialects.aiex import * | ||
from aie.dialects.scf import * | ||
from aie.extras.context import mlir_mod_ctx | ||
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def my_eltwise_mul(): | ||
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word_size_in = 2 | ||
N = 65536 | ||
N_in_bytes = N * word_size_in | ||
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A_sz_in_i32s = N_in_bytes // 4 | ||
B_sz_in_i32s = N_in_bytes // 4 | ||
C_sz_in_i32s = N_in_bytes // 4 | ||
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# Tile sizes | ||
n = 1024 | ||
N_div_n = N // n | ||
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n_cores = 2 | ||
tiles = N_div_n // n_cores | ||
buffer_depth = 2 | ||
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with mlir_mod_ctx() as ctx: | ||
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@device(AIEDevice.ipu) | ||
def device_body(): | ||
memRef_ty = T.memref(n, T.bf16()) | ||
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# Type used in the tile memory | ||
memRef_A_ty = T.memref(n, T.bf16()) | ||
memRef_B_ty = T.memref(n, T.bf16()) | ||
memRef_C_ty = T.memref(n, T.bf16()) | ||
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# Type used in the memory tile which aggregates across the 4 cores | ||
memRef_A_MT_ty = T.memref(n * n_cores, T.bf16()) | ||
memRef_B_MT_ty = T.memref(n * n_cores, T.bf16()) | ||
memRef_C_MT_ty = T.memref(n * n_cores, T.bf16()) | ||
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# AIE Core Function declarations | ||
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eltwise_mul_bf16_scalar = external_func( | ||
"eltwise_mul_bf16_scalar", inputs=[memRef_ty, memRef_ty, memRef_ty] | ||
) | ||
eltwise_mul_bf16_vector = external_func( | ||
"eltwise_mul_bf16_vector", inputs=[memRef_ty, memRef_ty, memRef_ty] | ||
) | ||
# elwise_int32 = external_func("scale_int32", inputs=[memRef_ty, memRef_ty]) | ||
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# Tile declarations | ||
ShimTile = tile(0, 0) | ||
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MemTile = tile(0, 1) | ||
cores = [tile(0, 2 + i) for i in range(n_cores)] | ||
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inA_fifo_names = [f"memA{i}" for i in range(n_cores)] | ||
inB_fifo_names = [f"memB{i}" for i in range(n_cores)] | ||
outC_fifo_names = [f"memC{i}" for i in range(n_cores)] | ||
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inA_fifos = {} | ||
inB_fifos = {} | ||
outC_fifos = {} | ||
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# AIE-array data movement with object fifos | ||
# Input A | ||
inA = object_fifo("inA", ShimTile, MemTile, buffer_depth, memRef_A_MT_ty) | ||
for i in range(n_cores): | ||
inA_fifos[inA_fifo_names[i]] = object_fifo( | ||
inA_fifo_names[i], MemTile, cores[i], buffer_depth, memRef_A_ty | ||
) | ||
object_fifo_link(inA, inA_fifo_names) | ||
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# Input B | ||
inB = object_fifo("inB", ShimTile, MemTile, buffer_depth, memRef_B_MT_ty) | ||
for i in range(n_cores): | ||
inB_fifos[inB_fifo_names[i]] = object_fifo( | ||
inB_fifo_names[i], MemTile, cores[i], buffer_depth, memRef_B_ty | ||
) | ||
object_fifo_link(inB, inB_fifo_names[0:n_cores]) | ||
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# Output C | ||
for i in range(n_cores): | ||
outC_fifos[outC_fifo_names[i]] = object_fifo( | ||
outC_fifo_names[i], cores[i], MemTile, buffer_depth, memRef_C_ty | ||
) | ||
outC = object_fifo("outC", MemTile, ShimTile, buffer_depth, memRef_C_MT_ty) | ||
object_fifo_link(outC_fifo_names[0:n_cores], outC) | ||
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# Set up compute tiles | ||
for i in range(n_cores): | ||
# Compute tile i | ||
@core(cores[i], "mul.o") | ||
def core_body(): | ||
for _ in for_(0xFFFFFFFF): | ||
for _ in for_(tiles): | ||
elem_out = outC_fifos[outC_fifo_names[i]].acquire( | ||
ObjectFifoPort.Produce, 1 | ||
) | ||
elem_in_a = inA_fifos[inA_fifo_names[i]].acquire( | ||
ObjectFifoPort.Consume, 1 | ||
) | ||
elem_in_b = inB_fifos[inB_fifo_names[i]].acquire( | ||
ObjectFifoPort.Consume, 1 | ||
) | ||
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call( | ||
eltwise_mul_bf16_vector, | ||
[elem_in_a, elem_in_b, elem_out], | ||
) | ||
inA_fifos[inA_fifo_names[i]].release( | ||
ObjectFifoPort.Consume, 1 | ||
) | ||
inB_fifos[inB_fifo_names[i]].release( | ||
ObjectFifoPort.Consume, 1 | ||
) | ||
outC_fifos[outC_fifo_names[i]].release( | ||
ObjectFifoPort.Produce, 1 | ||
) | ||
yield_([]) | ||
yield_([]) | ||
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# To/from AIE-array data movement | ||
tensor_ty = T.memref(N, T.i32()) | ||
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@FuncOp.from_py_func(tensor_ty, tensor_ty, tensor_ty) | ||
def sequence(A, B, C): | ||
ipu_dma_memcpy_nd( | ||
metadata="outC", bd_id=0, mem=C, sizes=[1, 1, 1, C_sz_in_i32s] | ||
) | ||
ipu_dma_memcpy_nd( | ||
metadata="inA", bd_id=1, mem=A, sizes=[1, 1, 1, A_sz_in_i32s] | ||
) | ||
ipu_dma_memcpy_nd( | ||
metadata="inB", bd_id=2, mem=B, sizes=[1, 1, 1, B_sz_in_i32s] | ||
) | ||
ipu_sync(column=0, row=0, direction=0, channel=0) | ||
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print(ctx.module) | ||
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my_eltwise_mul() |
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