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programming_examples/basic/passthrough_kernel/CMakeLists.txt
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# This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
# (c) Copyright 2023 Xilinx Inc. | ||
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# parameters | ||
# -DBOOST_ROOT: Path to Boost install | ||
# -DOpenCV_DIR: Path to OpenCV install | ||
# -DXRT_INC_DIR: Full path to src/runtime_src/core/include in XRT cloned repo | ||
# -DXRT_LIB_DIR: Path to xrt_coreutil.lib | ||
# -DTARGET_NAME: Target name to be built | ||
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# cmake needs this line | ||
cmake_minimum_required(VERSION 3.1) | ||
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find_program(WSL NAMES powershell.exe) | ||
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if (NOT WSL) | ||
set(BOOST_ROOT /usr/include/boost CACHE STRING "Path to Boost install") | ||
set(XRT_INC_DIR /opt/xilinx/xrt/include CACHE STRING "Path to XRT cloned repo") | ||
set(XRT_LIB_DIR /opt/xilinx/xrt/lib CACHE STRING "Path to xrt_coreutil.lib") | ||
else() | ||
set(BOOST_ROOT C:/Technical/thirdParty/boost_1_83_0 CACHE STRING "Path to Boost install") | ||
set(XRT_INC_DIR C:/Technical/XRT/src/runtime_src/core/include CACHE STRING "Path to XRT cloned repo") | ||
set(XRT_LIB_DIR C:/Technical/xrtIPUfromDLL CACHE STRING "Path to xrt_coreutil.lib") | ||
endif () | ||
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set(PASSTHROUGH_SIZE 4096 CACHE STRING "size") | ||
set(TARGET_NAME test CACHE STRING "Target to be built") | ||
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SET (ProjectName ${TARGET_NAME}) | ||
SET (currentTarget ${TARGET_NAME}) | ||
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if ( WSL ) | ||
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY_RELEASE ${CMAKE_BINARY_DIR}) | ||
endif () | ||
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project(${ProjectName}) | ||
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# Find packages | ||
find_package(Boost REQUIRED) | ||
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add_executable(${currentTarget} | ||
${CMAKE_CURRENT_SOURCE_DIR}/../../utils/xrtUtils.cpp | ||
test.cpp | ||
) | ||
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target_compile_definitions(${currentTarget} PUBLIC | ||
PASSTHROUGH_SIZE=${PASSTHROUGH_SIZE} | ||
DISABLE_ABI_CHECK=1 | ||
) | ||
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target_include_directories (${currentTarget} PUBLIC | ||
${CMAKE_CURRENT_SOURCE_DIR}/../../utils | ||
${XRT_INC_DIR} | ||
${Boost_INCLUDE_DIRS} | ||
) | ||
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target_link_directories(${currentTarget} PUBLIC | ||
${XRT_LIB_DIR} | ||
${Boost_LIBRARY_DIRS} | ||
) | ||
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if (NOT WSL) | ||
target_link_libraries(${currentTarget} PUBLIC | ||
xrt_coreutil | ||
boost_program_options | ||
boost_filesystem | ||
) | ||
else() | ||
target_link_libraries(${currentTarget} PUBLIC | ||
xrt_coreutil | ||
) | ||
endif() |
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##===- Makefile -----------------------------------------------------------===## | ||
# | ||
# This file licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
##===----------------------------------------------------------------------===## | ||
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include ../makefile-common | ||
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VPATH := ../../../aie_kernels/aie_generic | ||
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PASSTHROUGH_SIZE = 4096 | ||
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targetname = passthrough_kernel | ||
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.PHONY: all template clean | ||
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all: build/final_${PASSTHROUGH_SIZE}.xclbin | ||
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build/aie2_lineBased_8b_${PASSTHROUGH_SIZE}.mlir: aie2.py | ||
mkdir -p ${@D} | ||
python3 $< ${PASSTHROUGH_SIZE} > $@ | ||
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build/passThrough.cc.o: passThrough.cc | ||
mkdir -p ${@D} | ||
cd ${@D} && xchesscc_wrapper ${CHESSCCWRAP2_FLAGS} -DBIT_WIDTH=8 -c $(<:%=../%) -o ${@F} | ||
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build/final_${PASSTHROUGH_SIZE}.xclbin: build/aie2_lineBased_8b_${PASSTHROUGH_SIZE}.mlir build/passThrough.cc.o | ||
mkdir -p ${@D} | ||
cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host \ | ||
--xclbin-name=${@F} --ipu-insts-name=insts.txt $(<:%=../%) | ||
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${targetname}.exe: test.cpp | ||
rm -rf _build | ||
mkdir -p _build | ||
cd _build && ${powershell} cmake .. -DTARGET_NAME=${targetname} -DPASSTHROUGH_SIZE=${PASSTHROUGH_SIZE} | ||
cd _build && ${powershell} cmake --build . --config Release | ||
ifeq "${powershell}" "powershell.exe" | ||
cp _build/${targetname}.exe $@ | ||
else | ||
cp _build/${targetname} $@ | ||
endif | ||
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run: ${targetname}.exe build/final_${PASSTHROUGH_SIZE}.xclbin build/insts.txt | ||
${powershell} ./$< -x build/final_${PASSTHROUGH_SIZE}.xclbin -i build/insts.txt -k MLIR_AIE | ||
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clean: | ||
rm -rf build _build ${targetname}.exe |
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# | ||
# This file is licensed under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
# (c) Copyright 2023 AMD Inc. | ||
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import sys | ||
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from aie.dialects.aie import * | ||
from aie.dialects.aiex import * | ||
from aie.dialects.scf import * | ||
from aie.extras.context import mlir_mod_ctx | ||
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width = 1024 | ||
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if len(sys.argv) == 2: | ||
width = int(sys.argv[1]) | ||
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lineWidthInBytes = width | ||
lineWidthInInt32s = lineWidthInBytes // 4 | ||
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enableTrace = False | ||
traceSizeInBytes = 8192 | ||
traceSizeInInt32s = traceSizeInBytes // 4 | ||
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def passThroughAIE2(): | ||
with mlir_mod_ctx() as ctx: | ||
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@device(AIEDevice.ipu) | ||
def device_body(): | ||
# define types | ||
line_ty = T.memref(lineWidthInBytes, T.ui8()) | ||
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# AIE Core Function declarations | ||
passThroughLine = external_func( | ||
"passThroughLine", inputs=[line_ty, line_ty, T.i32()] | ||
) | ||
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# Tile declarations | ||
ShimTile = tile(0, 0) | ||
ComputeTile2 = tile(0, 2) | ||
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if enableTrace: | ||
flow(ComputeTile2, "Trace", 0, ShimTile, "DMA", 1) | ||
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# AIE-array data movement with object fifos | ||
of_in = object_fifo("in", ShimTile, ComputeTile2, 2, line_ty) | ||
of_out = object_fifo("out", ComputeTile2, ShimTile, 2, line_ty) | ||
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# Set up compute tiles | ||
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# Compute tile 2 | ||
@core(ComputeTile2, "passThrough.cc.o") | ||
def core_body(): | ||
for _ in for_(sys.maxsize): | ||
elemOut = of_out.acquire(ObjectFifoPort.Produce, 1) | ||
elemIn = of_in.acquire(ObjectFifoPort.Consume, 1) | ||
call(passThroughLine, [elemIn, elemOut, width]) | ||
of_in.release(ObjectFifoPort.Consume, 1) | ||
of_out.release(ObjectFifoPort.Produce, 1) | ||
yield_([]) | ||
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# print(ctx.module.operation.verify()) | ||
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tensorSize = width | ||
tensorSizeInInt32s = tensorSize // 4 | ||
tensor_ty = T.memref(tensorSizeInInt32s, T.i32()) | ||
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@FuncOp.from_py_func(tensor_ty, tensor_ty, tensor_ty) | ||
def sequence(inTensor, outTensor, notUsed): | ||
if enableTrace: | ||
# Trace output | ||
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# Trace_Event0, Trace_Event1: Select which events to trace. | ||
# Note that the event buffers only appear to be transferred to DDR in | ||
# bursts of 256 bytes. If less than 256 bytes are written, you may not | ||
# see trace output, or only see it on the next iteration of your | ||
# kernel invocation, as the buffer gets filled up. Note that, even | ||
# though events are encoded as 4 byte words, it may take more than 64 | ||
# events to fill the buffer to 256 bytes and cause a flush, since | ||
# multiple repeating events can be 'compressed' by the trace mechanism. | ||
# In order to always generate sufficient events, we add the "assert | ||
# TRUE" event to one slot, which fires every cycle, and thus fills our | ||
# buffer quickly. | ||
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# Some events: | ||
# TRUE (0x01) | ||
# STREAM_STALL (0x18) | ||
# LOCK_STALL (0x1A) | ||
# EVENTS_CORE_INSTR_EVENT_1 (0x22) | ||
# EVENTS_CORE_INSTR_EVENT_0 (0x21) | ||
# INSTR_VECTOR (0x25) Core executes a vecotr MAC, ADD or compare instruction | ||
# INSTR_LOCK_ACQUIRE_REQ (0x2C) Core executes a lock acquire instruction | ||
# INSTR_LOCK_RELEASE_REQ (0x2D) Core executes a lock release instruction | ||
# EVENTS_CORE_PORT_RUNNING_1 (0x4F) | ||
# EVENTS_CORE_PORT_RUNNING_0 (0x4B) | ||
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# Trace_Event0 (4 slots) | ||
IpuWrite32(0, 2, 0x340E0, 0x4B222125) | ||
# Trace_Event1 (4 slots) | ||
IpuWrite32(0, 2, 0x340E4, 0x2D2C1A4F) | ||
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# Event slots as configured above: | ||
# 0: Kernel executes vector instruction | ||
# 1: Event 0 -- Kernel starts | ||
# 2: Event 1 -- Kernel done | ||
# 3: Port_Running_0 | ||
# 4: Port_Running_1 | ||
# 5: Lock Stall | ||
# 6: Lock Acquire Instr | ||
# 7: Lock Release Instr | ||
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# Stream_Switch_Event_Port_Selection_0 | ||
# This is necessary to capture the Port_Running_0 and Port_Running_1 events | ||
IpuWrite32(0, 2, 0x3FF00, 0x121) | ||
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# Trace_Control0: Define trace start and stop triggers. Set start event TRUE. | ||
IpuWrite32(0, 2, 0x340D0, 0x10000) | ||
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# Start trace copy out. | ||
IpuWriteBdShimTile( | ||
bd_id=3, | ||
buffer_length=traceSizeInBytes, | ||
buffer_offset=tensorSize, | ||
enable_packet=0, | ||
out_of_order_id=0, | ||
packet_id=0, | ||
packet_type=0, | ||
column=0, | ||
column_num=1, | ||
d0_stride=0, | ||
d0_wrap=0, | ||
d1_stride=0, | ||
d1_wrap=0, | ||
d2_stride=0, | ||
ddr_id=2, | ||
iteration_current=0, | ||
iteration_stride=0, | ||
iteration_wrap=0, | ||
lock_acq_enable=0, | ||
lock_acq_id=0, | ||
lock_acq_val=0, | ||
lock_rel_id=0, | ||
lock_rel_val=0, | ||
next_bd=0, | ||
use_next_bd=0, | ||
valid_bd=1, | ||
) | ||
IpuWrite32(0, 0, 0x1D20C, 0x3) | ||
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ipu_dma_memcpy_nd( | ||
metadata="in", | ||
bd_id=0, | ||
mem=inTensor, | ||
sizes=[1, 1, 1, tensorSizeInInt32s], | ||
) | ||
ipu_dma_memcpy_nd( | ||
metadata="out", | ||
bd_id=1, | ||
mem=outTensor, | ||
sizes=[1, 1, 1, tensorSizeInInt32s], | ||
) | ||
ipu_sync(column=0, row=0, direction=0, channel=0) | ||
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print(ctx.module) | ||
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passThroughAIE2() |
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