[AIE] Add Pure trait to TileOp (#1315)

Xilinx · Apr 19, 2024 · d065e66 · d065e66
1 parent 9dbd283
commit d065e66
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diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td
@@ -67,6 +67,7 @@ def AIE_DeviceOp: AIE_Op<"device", [
 }
 
 def AIE_TileOp: AIE_Op<"tile", [
+    Pure,
     FlowEndPoint,
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     DeclareOpInterfaceMethods<InferTypeOpInterface>

diff --git a/test/dialect/AIE/tileop_cse.mlir b/test/dialect/AIE/tileop_cse.mlir
@@ -0,0 +1,26 @@
+//===- tileop_cse.mlir -----------------------------------------*- MLIR -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// Copyright (C) 2024, Advanced Micro Devices, Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// RUN: aie-opt --split-input-file --pass-pipeline="builtin.module(cse)" %s | FileCheck %s
+
+// CHECK: %[[TILE1:.*]] = aie.tile(1, 1)
+// CHECK-NOT: %[[TILE2:.*]] = aie.tile(1, 1)
+// CHECK: %[[CORE1:.*]] = aie.core(%[[TILE1]])
+// CHECK: %[[CORE2:.*]] = aie.core(%[[TILE1]])
+module {
+  %tile_1 = aie.tile(1, 1)
+  %tile_2 = aie.tile(1, 1)
+  %core_1 = aie.core(%tile_1) {
+    aie.end
+  }
+  %core_2 = aie.core(%tile_2) {
+    aie.end
+  }
+}