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add more of the api boilerplate
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@fifield
fifield committed May 21, 2024
1 parent c827a7d commit e5f8921
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85 changes: 85 additions & 0 deletions include/aie-c/TargetModel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,91 @@ MLIR_CAPI_EXPORTED int aieTargetModelRows(AieTargetModel targetModel);
/// Returns true if this is an NPU target model.
MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED bool aieTargetModelIsCoreTile(AieTargetModel targetModel,
int col, int row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsMemTile(AieTargetModel targetModel,
int col, int row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel,
int col, int row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsShimPLTile(AieTargetModel targetModel,
int col, int row);

MLIR_CAPI_EXPORTED bool
aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col, int row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsInternal(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsWest(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsEast(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsNorth(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsSouth(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsMemWest(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsMemEast(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsMemNorth(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool aieTargetModelIsMemSouth(AieTargetModel targetModel,
int src_col, int src_row,
int dst_col, int dst_row);

MLIR_CAPI_EXPORTED bool
aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetLocalMemorySize(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetNumLocks(AieTargetModel targetModel, int col, int row);

MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel,
int col, int row);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetNumMemTileRows(AieTargetModel targetModel);

MLIR_CAPI_EXPORTED uint32_t
aieTargetModelGetMemTileSize(AieTargetModel targetModel);

/// Returns true if this is an NPU target model.
MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel);

#ifdef __cplusplus
}
#endif
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109 changes: 109 additions & 0 deletions lib/CAPI/TargetModel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,115 @@ int aieTargetModelRows(AieTargetModel targetModel) {
return unwrap(targetModel).rows();
}

bool aieTargetModelIsCoreTile(AieTargetModel targetModel, int col, int row) {
return unwrap(targetModel).isCoreTile(col, row);
}

bool aieTargetModelIsMemTile(AieTargetModel targetModel, int col, int row) {
return unwrap(targetModel).isMemTile(col, row);
}

bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel, int col, int row) {
return unwrap(targetModel).isShimNOCTile(col, row);
}

bool aieTargetModelIsShimPLTile(AieTargetModel targetModel, int col, int row) {
return unwrap(targetModel).isShimPLTile(col, row);
}

bool aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col,
int row) {
return unwrap(targetModel).isShimNOCorPLTile(col, row);
}

bool aieTargetModelIsInternal(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel).isInternal(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsWest(AieTargetModel targetModel, int src_col, int src_row,
int dst_col, int dst_row) {
return unwrap(targetModel).isWest(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsEast(AieTargetModel targetModel, int src_col, int src_row,
int dst_col, int dst_row) {
return unwrap(targetModel).isEast(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsNorth(AieTargetModel targetModel, int src_col, int src_row,
int dst_col, int dst_row) {
return unwrap(targetModel).isNorth(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsSouth(AieTargetModel targetModel, int src_col, int src_row,
int dst_col, int dst_row) {
return unwrap(targetModel).isSouth(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsMemWest(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel).isMemWest(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsMemEast(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel).isMemEast(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsMemNorth(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel).isMemNorth(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsMemSouth(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel).isMemSouth(src_col, src_row, dst_col, dst_row);
}

bool aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col,
int src_row, int dst_col, int dst_row) {
return unwrap(targetModel)
.isLegalMemAffinity(src_col, src_row, dst_col, dst_row);
}

uint32_t aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel) {
return unwrap(targetModel).getMemSouthBaseAddress();
}

uint32_t aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel) {
return unwrap(targetModel).getMemNorthBaseAddress();
}

uint32_t aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel) {
return unwrap(targetModel).getMemEastBaseAddress();
}

uint32_t aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel) {
return unwrap(targetModel).getMemWestBaseAddress();
}

uint32_t aieTargetModelGetLocalMemorySize(AieTargetModel targetModel) {
return unwrap(targetModel).getLocalMemorySize();
}

uint32_t aieTargetModelGetNumLocks(AieTargetModel targetModel, int col,
int row) {
return unwrap(targetModel).getNumLocks(col, row);
}

uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel, int col, int row) {
return unwrap(targetModel).getNumBDs(col, row);
}

uint32_t aieTargetModelGetNumMemTileRows(AieTargetModel targetModel) {
return unwrap(targetModel).getNumMemTileRows();
}

uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel) {
return unwrap(targetModel).getMemTileSize();
}

bool aieTargetModelIsNPU(AieTargetModel targetModel) {
return unwrap(targetModel).isNPU();
}
128 changes: 128 additions & 0 deletions python/AIEMLIRModule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -167,6 +167,134 @@ PYBIND11_MODULE(_aie, m) {
"rows",
[](PyAieTargetModel &self) { return aieTargetModelRows(self.get()); },
"Get the number of rows in the device.")
.def("is_core_tile",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelIsCoreTile(self.get(), col, row);
})
.def("is_mem_tile",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelIsMemTile(self.get(), col, row);
})
.def("is_shim_noc_tile",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelIsShimNOCTile(self.get(), col, row);
})
.def("is_shim_pl_tile",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelIsShimPLTile(self.get(), col, row);
})
.def("is_shim_noc_or_pl_tile",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelIsShimNOCorPLTile(self.get(), col, row);
})
// .def("is_valid_tile")
// .def("is_valid_trace_master")
// .def("get_mem_west")
// .def("get_mem_east")
// .def("get_mem_north")
// .def("get_mem_south")
.def("is_internal",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsInternal(self.get(), src_col, src_row,
dst_col, dst_row);
})
.def("is_west",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsWest(self.get(), src_col, src_row, dst_col,
dst_row);
})
.def("is_east",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsEast(self.get(), src_col, src_row, dst_col,
dst_row);
})
.def("is_north",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsNorth(self.get(), src_col, src_row, dst_col,
dst_row);
})
.def("is_south",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsSouth(self.get(), src_col, src_row, dst_col,
dst_row);
})
.def("is_mem_west",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsMemWest(self.get(), src_col, src_row,
dst_col, dst_row);
})
.def("is_mem_east",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsMemEast(self.get(), src_col, src_row,
dst_col, dst_row);
})
.def("is_mem_north",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsMemNorth(self.get(), src_col, src_row,
dst_col, dst_row);
})
.def("is_mem_south",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsMemSouth(self.get(), src_col, src_row,
dst_col, dst_row);
})
.def("is_legal_mem_affinity",
[](PyAieTargetModel &self, int src_col, int src_row, int dst_col,
int dst_row) {
return aieTargetModelIsLegalMemAffinity(self.get(), src_col,
src_row, dst_col, dst_row);
})
//.def("get_mem_internal_base_address")
.def("get_mem_west_base_address",
[](PyAieTargetModel &self) {
return aieTargetModelGetMemWestBaseAddress(self.get());
})
.def("get_mem_east_base_address",
[](PyAieTargetModel &self) {
return aieTargetModelGetMemEastBaseAddress(self.get());
})
.def("get_mem_north_base_address",
[](PyAieTargetModel &self) {
return aieTargetModelGetMemNorthBaseAddress(self.get());
})
.def("get_mem_south_base_address",
[](PyAieTargetModel &self) {
return aieTargetModelGetMemSouthBaseAddress(self.get());
})
.def("get_local_memory_size",
[](PyAieTargetModel &self) {
return aieTargetModelGetLocalMemorySize(self.get());
})
.def("get_num_locks",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelGetNumLocks(self.get(), col, row);
})
.def("get_num_bds",
[](PyAieTargetModel &self, int col, int row) {
return aieTargetModelGetNumBDs(self.get(), col, row);
})
.def("get_num_mem_tile_rows",
[](PyAieTargetModel &self) {
return aieTargetModelGetNumMemTileRows(self.get());
})
.def("get_mem_tile_size",
[](PyAieTargetModel &self) {
return aieTargetModelGetMemTileSize(self.get());
})
// .def("get_num_dest_switchbox_connections", int col, int row)
// .def("get_num_source_switchbox_connections", int col, int row)
// .def("get_num_dest_shim_mux_connections", int col, int row)
// .def("get_num_source_shim_mux_connections", int col, int row)
// .def("is_legal_memtile_connection")
.def("is_npu", [](PyAieTargetModel &self) {
return aieTargetModelIsNPU(self.get());
});
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