scale fixes for resnet (#1506)

Xilinx · May 22, 2024 · f46ea61 · f46ea61
1 parent 37ef519
commit f46ea61
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Showing 3 changed files with 22 additions and 32 deletions.
diff --git a/programming_examples/ml/resnet/layers_conv2_x/aie.mlir b/programming_examples/ml/resnet/layers_conv2_x/aie.mlir
@@ -6,7 +6,7 @@
 //===----------------------------------------------------------------------===//
 
 module {
-aie.device(npu) {
+aie.device(npu1_3col) {
 
   //shim
   %tile00 = aie.tile(0, 0)

diff --git a/programming_examples/ml/resnet/layers_conv2_x/aie2.py b/programming_examples/ml/resnet/layers_conv2_x/aie2.py
@@ -580,7 +580,7 @@ def core_body():
 
                 @core(cores[i][1], "conv2dk3.o")
                 def core_body():
-                    scale = 11
+                    scale = 1
                     for _ in for_(sys.maxsize):
 
                         # acquire weights and rtps once
@@ -697,7 +697,7 @@ def core_body():
 
                 @core(cores[i][3], "conv2dk3.o")
                 def core_body():
-                    scale = 11
+                    scale = 1
                     for _ in for_(sys.maxsize):
 
                         # acquire weights and rtps once
@@ -927,33 +927,24 @@ def core_body():
             )
             def sequence(inputFromL3, weightsFromL3, outputToL3):
 
-                # for c, col in enumerate(rtp_name):
-                #     for r, row in enumerate(col):
-                #         NpuWriteRTPOp(row, col=c, row=r + 2, index=0, value=1)  # scale
-
-                # NpuWriteRTPOp("rtpComputeTile05", col=0, row=4, index=1, value=0)
-                # NpuWriteRTPOp("rtpComputeTile05", col=0, row=4, index=2, value=1)
-
-                # NpuWriteRTPOp("rtpComputeTile13", col=1, row=3, index=1, value=0)
-
-                # NpuWriteRTPOp("rtpComputeTile24", col=2, row=4, index=1, value=0)
-
-                # #     # write RTP parameters
-                # npuWriteRTPOp(
-                #     "rtpComputeTile02", col=0, row=2, index=0, value=1
-                # )  # scale
-                # npuWriteRTPOp(
-                #     "rtpComputeTile03", col=0, row=3, index=0, value=1
-                # )  # scale
-                # npuWriteRTPOp(
-                #     "rtpComputeTile05", col=0, row=5, index=0, value=1
-                # )  # scale
-                # npuWriteRTPOp(
-                #     "rtpComputeTile04", col=0, row=4, index=0, value=1
-                # )  # scale: conv1x1 with the same scale as the input so we match the scaling factor of output after conv1x1 and the initial input
-                # npuWriteRTPOp(
-                #     "rtpComputeTile04", col=0, row=4, index=1, value=0
-                # )  # skip_scale
+                NpuWriteRTPOp("rtpComputeTile02", col=0, row=2, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile03", col=0, row=3, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile04", col=0, row=5, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile05", col=0, row=4, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile05", col=0, row=4, index=1, value=0)
+                NpuWriteRTPOp("rtpComputeTile05", col=0, row=4, index=2, value=1)
+
+                NpuWriteRTPOp("rtpComputeTile15", col=1, row=5, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile14", col=1, row=4, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile12", col=1, row=2, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile13", col=1, row=3, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile13", col=1, row=3, index=1, value=0)
+
+                NpuWriteRTPOp("rtpComputeTile22", col=2, row=2, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile23", col=2, row=3, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile25", col=2, row=5, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile24", col=2, row=4, index=0, value=1)
+                NpuWriteRTPOp("rtpComputeTile24", col=2, row=4, index=1, value=0)
 
                 npu_dma_memcpy_nd(
                     metadata="act1_00_02_01",

diff --git a/programming_examples/ml/resnet/layers_conv2_x/run_makefile.lit b/programming_examples/ml/resnet/layers_conv2_x/run_makefile.lit
@@ -1,8 +1,7 @@
 // (c) Copyright 2024 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// This test is disabled due to random failures on gihub CI
-// REQUIRES: ryzen_ai, chess, torch, has_random_failures
+// REQUIRES: ryzen_ai, chess, torch
 //
 // RUN: make -f %S/Makefile clean
 // RUN: make -f %S/Makefile