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abhinav-kumar-ece/README.md

abhinav@github ~ $ ./contributions.sh



abhinav@github ~ $ whoami

abhinav@github ~ $ cat status.md

2026 ECE graduate (BBAU Lucknow), job-hunting across two tracks: VLSI/RTL Design & Verification (primary) and Data Analytics (secondary). Taped out a 5-stage RV32I RISC-V core from RTL to GDSII on the sky130A PDK and shipped an open-source Verilog linter. Everything below is labeled by actual status — nothing here is padded.


abhinav@github ~ $ ls shipped/

🖥️ pipelined-riscv-core — 5-stage pipelined RV32I core (IF/ID/EX/MEM/WB) with forwarding and hazard detection, taken through full RTL-to-GDSII on the sky130A PDK using LibreLane. Two real RTL bugs found and fixed during the flow.

  • Post-route STA: WNS = 0.0 ns, worst hold slack = +0.337 ns, Fmax = 194.97 MHz
  • Paper on Zenodo; submitted to IJCAD (Inderscience) — currently under peer review

🧠 rtl-intent-checker — Python/pyverilog semantic linter for Verilog, MIT licensed. 7 checks (if-without-else, missing-default-case, blocking-in-seq, nonblocking-in-comb, unused-signal, undriven-signal, multi-driver signal). Packaged as an installable Python package plus a PyInstaller Windows .exe, with a GitHub Pages landing page.

🏠 fpga-home-safety-system — Final-year capstone: sensor-driven FPGA safety/automation system (gas, air quality, temp/humidity, flame, water level) benchmarked across four Xilinx FPGA families, sub-5ns propagation delay, 1% logic utilization. Paper under peer review at IJCAD.


abhinav@github ~ $ ls in-progress/

  • UVM verification environment for the pipelined RISC-V core — 11-file UVM-1.2 testbench written (driver, monitor, scoreboard, sequencer, agent), not yet executed due to EDA Playground access constraints
  • Multi-PDK UART comparison — sky130A run clean, gf180mcuD has a setup violation at the slow-slow corner (real caveat, not glossed over)

abhinav@github ~ $ cat toolchain.md

Chip/RTL: Verilog · SystemVerilog · RV32I ISA · 5-stage pipelining · hazard/forwarding logic · FSM design Verification: Functional verification · self-checking testbenches · STA · timing closure · UVM (in progress) EDA/Flow: Vivado · Xilinx ISE/XSim · LibreLane (sky130A, gf180mcuD) · KLayout · Cadence (basic) · QuestaSim Also: Python (scripting/test automation) · SQL · BigQuery · Power BI · Excel


📫 abhinavkumar47332@gmail.com · LinkedIn · Vaishali, Bihar, India

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