Added monitor info when assertion gets triggered

Signed-off-by: Anderson Ignacio da Silva <anderson@aignacio.com>
aignacio · Sep 7, 2024 · a164bfc · a164bfc
1 parent abf839d
commit a164bfc
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Showing 3 changed files with 21 additions and 20 deletions.
diff --git a/cocotbext/ahb/ahb_monitor.py b/cocotbext/ahb/ahb_monitor.py
@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 27.10.2023
-# Last Modified Date: 15.06.2024
+# Last Modified Date: 07.09.2024
 import cocotb
 import logging
 import random
@@ -85,7 +85,7 @@ async def _monitor_recv(self):
                             pass
                         else:
                             raise AssertionError(
-                                "AHB PROTOCOL VIOLATION: Master.hwdata signal should not change before slave.hready == 1"
+                                f"[{self.bus.name}/{self.name}] AHB PROTOCOL VIOLATION: Master.hwdata signal should not change before slave.hready == 1"
                             )
 
                 # Previous cycle we started a txn and slave was ready, and now it is still ready
@@ -97,7 +97,7 @@ async def _monitor_recv(self):
                         slave_error_prev == 0
                     ):
                         raise AssertionError(
-                            "AHB PROTOCOL VIOLATION: Slave is not following the 2-cyle error response \
+                            f"[{self.bus.name}/{self.name}] AHB PROTOCOL VIOLATION: Slave is not following the 2-cyle error response \
                                     - ARM IHI 0033B.b (ID102715) - Section 5.1.3"
                         )
 
@@ -231,7 +231,7 @@ def _check_signals(self, stable):
                     pass
                 else:
                     raise AssertionError(
-                        f"AHB PROTOCOL VIOLATION: Master.{signal} signal should not change before slave.hready == 1"
+                        f"[{self.bus.name}/{self.name}] AHB PROTOCOL VIOLATION: Master.{signal} signal should not change before slave.hready == 1"
                     )
 
 

diff --git a/cocotbext/ahb/version.py b/cocotbext/ahb/version.py
@@ -1 +1 @@
-__version__ = "0.3.3"
+__version__ = "0.3.4"
diff --git a/docs_utils/template.gtkw b/docs_utils/template.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Sun Dec 10 16:59:29 2023
+[*] Fri Sep  6 22:51:52 2024
 [*]
-[dumpfile] "run_dir/sim_build_icarus_test_ahb_lite_sram_no_errors/ahb_template.fst"
-[dumpfile_mtime] "Sun Dec 10 16:52:49 2023"
-[dumpfile_size] 1031
-[savefile] "/Users/aignacio/projects/cocotbext-ahb/docs_utils/template.gtkw"
+[dumpfile] "run_dir/sim_build_icarus_test_ahb_lite_monitor_scoreboard_data_width_32_bits/ahb_template.fst"
+[dumpfile_mtime] "Fri Sep  6 22:50:43 2024"
+[dumpfile_size] 11612
+[savefile] "docs_utils/template.gtkw"
 [timestart] 0
-[size] 2680 1028
+[size] 1896 1028
 [pos] 2007 278
-*-14.146851 30000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-15.647337 32000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 253
 [signals_width] 263
 [sst_expanded] 1
@@ -23,21 +23,22 @@ ahb_template.hclk
 ahb_template.hsel
 @22
 ahb_template.haddr[31:0]
-@29
-ahb_template.hwrite
 @28
+ahb_template.hwrite
+ahb_template.hready_in
 ahb_template.hsize[2:0]
+ahb_template.hburst[2:0]
 @100000028
 ahb_template.htrans[1:0]
-@28
-ahb_template.hready_in
-ahb_template.hburst[2:0]
 @22
-ahb_template.hrdata[31:0]
-@28
+ahb_template.hwdata[31:0]
+@200
+-
+@29
 ahb_template.hready
+@28
 ahb_template.hresp
 @22
-ahb_template.hwdata[31:0]
+ahb_template.hrdata[31:0]
 [pattern_trace] 1
 [pattern_trace] 0