Start building base classes

Signed-off-by: Anderson Ignacio <anderson@aignacio.com>

.gitignore

@@ -133,3 +133,4 @@ dmypy.json
 output
 run_dir/
 .nox/*
+.DS_Store

cocotbext/ahb/__init__.py

@@ -4,5 +4,6 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson Ignacio da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 02.10.2023
-# Last Modified Date: 05.10.2023
+# Last Modified Date: 07.10.2023
 from .amba_ahb import AHBLiteMaster
+from .amba_ahb import AHBBus

cocotbext/ahb/amba_ahb.py

@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson Ignacio da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 01.10.2023
-# Last Modified Date: 05.10.2023
+# Last Modified Date: 07.10.2023
 import cocotb
 import enum
 
@@ -49,6 +49,40 @@ class AHBWrite(enum.IntEnum):
     WRITE   = 0b0
     READ    = 0b1
 
+class AHBBus(Bus):
+    _signals = ["haddr", "hsize", "htrans", "hwdata",
+                "hrdata", "hwrite", "hready", "hresp"]
+
+    _optional_signals = ["hburst","hmastlock", "hprot", "hnonsec",
+                         "hexcl", "hmaster", "hexokay", "hsel"]
+
+    def __init__(self, entity: SimHandleBase=None, 
+                 prefix:str=None, clock:str=None, **kwargs: Any):
+        super().__init__(entity, prefix, self._signals, 
+                         optional_signals=self._optional_signals, **kwargs)
+        self.entity = entity
+        self.clock = clock
+        self.name = prefix if prefix is not None else entity._name+'_AHBBus' 
+        self._data_width = len(self.hwdata)
+        self._addr_width = len(self.haddr)
+
+    @property
+    def data_width(self):
+        return self._data_width
+
+    @property
+    def addr_width(self):
+        return self._addr_width
+
+    @classmethod
+    def from_entity(cls, entity, clock, **kwargs):
+        return cls(entity, '', clock, **kwargs)
+
+    @classmethod
+    def from_prefix(cls, entity, prefix, clock, **kwargs):
+        return cls(entity, prefix, clock, **kwargs)
+
+
 class AHBLiteMaster(BusDriver):
     _signals = ["haddr", "hsize", "htrans", "hwdata",
                 "hrdata", "hwrite", "hready", "hresp"]
@@ -57,8 +91,8 @@ class AHBLiteMaster(BusDriver):
                          "hexcl", "hmaster", "hexokay", "hsel"]
 
     def __init__(self, entity, name, clock, **kwargs):
-        BusDriver.__init__(self, entity, name, clock)
-        self.clock = clock
+        super().__init__(entity, name, clock)
+
         for signal in self._signals + self._optional_signals:
             if signal not in ["hready", "hresp", "hrdata"]:
                 try:
@@ -106,24 +140,3 @@ async def write(self, address: int, value: Union[int, Sequence[int]],
         # Data phase
         self.bus.hwdata.value = value
         await RisingEdge(self.clock)
-
-# class test(Bus):
-    # _signals = ["haddr", "hsize", "htrans", "hwdata",
-                # "hrdata", "hwrite", "hready", "hresp"]
-
-    # _optional_signals = ["hburst","hmastlock", "hprot", "hnonsec",
-                         # "hexcl", "hmaster", "hexokay", "hsel"]
-
-    # def __init__(self, entity, name, clock, **kwargs):
-        # self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
-        # super().__init__(entity, name, self._signals, optional_signals=self._optional_signals, **kwargs)
-
-        # self.clock = clock
-        # for signal in self._signals:
-            # if signal not in ["hready", "hresp", "hrdata"]:
-                # try:
-                    # default_value = 0
-                    # getattr(self.bus, signal).setimmediatevalue(default_value)
-                # except AttributeError:
-                    # pass
-

tests/dut/dut.v

@@ -11,6 +11,28 @@ module ahb_template #(
 )(
   input                       hclk,
   input                       hresetn,
+  //----------------------------------------
+  // SLAVE - IN
+  //---------------------------------------
+  // From master/interconnect to slave/decoder 
+  input                       hsel,
+  input   [(ADDR_WIDTH-1):0]  haddr,
+  input   [2:0]               hburst,
+  input                       hmastlock,
+  input   [6:0]               hprot,
+  input   [2:0]               hsize,
+  input                       hnonsec,
+  input                       hexcl,
+  input   [3:0]               hmaster,
+  input   [1:0]               htrans,
+  input   [(DATA_WIDTH-1):0]  hwdata,
+  input                       hwrite,
+  // From slave to interconnect/master 
+  output  [(DATA_WIDTH-1):0]  hrdata,
+  output                      hready,
+  output                      hresp,
+  output                      hexokay,
+
   //----------------------------------------
   // SLAVE - IN
   //---------------------------------------

tests/test_ahb_lite.py

@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson Ignacio da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 30.09.2023
-# Last Modified Date: 05.10.2023
+# Last Modified Date: 07.10.2023
 import random
 import cocotb
 import os
@@ -19,7 +19,7 @@
 from cocotb.triggers import ClockCycles
 from cocotb.regression import TestFactory
 from cocotb.clock import Clock
-from cocotbext.ahb import AHBLiteMaster
+from cocotbext.ahb import AHBLiteMaster, AHBBus
 
 @cocotb.coroutine
 async def setup_dut(dut, cycles):
@@ -30,12 +30,12 @@ async def setup_dut(dut, cycles):
 
 @cocotb.test()
 async def run_test(dut):
-    ahbMaster = AHBLiteMaster(dut, "slave", dut.hclk)
+    ahbMaster  = AHBBus(dut, "slave", dut.hclk)
+    ahbMaster1 = AHBBus.from_entity(dut, dut.hclk)
+    ahbMaster2 = AHBBus.from_prefix(dut, "slave", dut.hclk)
     await setup_dut(dut, cfg.RST_CYCLES) 
-    await ClockCycles(dut.hclk,10)
-    await ahbMaster.write(0x123,0xdeadbeef) 
-    await ClockCycles(dut.hclk,10)
-    await ahbMaster.write(0x456,0xbabebabe) 
+    # await ahbMaster.write(0x123,0xdeadbeef) 
+    # await ahbMaster.write(0x456,0xbabebabe) 
 
 def test_ahb_lite():
     """