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Copy tt-vga-fun's '11-ratioed.sch' as: csdac.sch
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algofoogle committed Aug 9, 2024
1 parent 97a6ad7 commit b45b2eb
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6 changes: 6 additions & 0 deletions .gitignore
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Expand Up @@ -9,3 +9,9 @@ test/sim_build
test/__pycache__/
test/results.xml
test/gate_level_netlist.v
*~
.*.swp
JUNK
sim/spice/sim_out/*.raw
xschem/simulation/*.raw

2 changes: 1 addition & 1 deletion src/project.v
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`default_nettype none

module tt_um_example (
module tt_um_algofoogle_tt08_vga_fun (
input wire VGND,
input wire VDPWR, // 1.8v power supply
input wire VAPWR, // 3.3v power supply
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1 change: 1 addition & 0 deletions xschem/.gitignore
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simulation/*.raw
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