RTL Design & Verification Engineer | VLSI | RISC-V | AMBA Protocols | UVM | FPGA ! RTL-to-GDSII ASIC Design

I am a hardware engineer obsessed with pushing the boundaries of computer architecture, silicon design, and edge AI. I graduated from CUET (B.Sc. ETE, VLSI Major) and am currently building digital systems at ADN Semiconductors and teaching VLSI at MIU. I love seeing logic gates come to life.

ADN Semiconductors Ltd. - Intern, RTL Design & Verification Engineer · June 2026 – Present

• Hands-on RTL design & verification across APB-UART, SPI, AXI4, DDR3, and RISC-V blocks in Verilog/SystemVerilog.
• Developed custom testbenches using AMD Xilinx Vivado & GTKWave; automated workflows via Makefiles in Linux.

Manarat International University (MIU) - VLSI Lecturer (Part-Time) · May 2026 – Present

• Delivering VLSI Design lectures and practical sessions for the EEE Department; developing quizzes, exams, and assessments.

EVPIX-RV32: Custom RISC-V SoC with IPU & TinyML Accelerator - My flagship project. A 32-bit, 5-stage pipelined RISC-V (RV32I) processor integrated with an Image Processing Unit (IPU) and TinyML Accelerator for real-time edge-vision AI.

• Verified via real Basys-3 AMD Artix-7 FPGA prototyping.
• Completed full RTL-to-GDSII ASIC flow using OpenROAD Flow Scripts with SkyWater 130-nm PDK.

APB Peripheral Subsystem & UVM Verification Suite - APB3/4 subsystem integrating UART, SPI, I2C, GPIO, Timers, PWM, WDT, and a Memory Controller with a full modular UVM environment, SVA assertions, and Makefile regression automation.

Common IP Library with OOP Testbenches & SVA - Parameterizable SystemVerilog IP library (RAMs, FIFOs, CDC Synchronizers, Arbiters) with class-based layered testbenches, bind-module SVA, and a two-tier Makefile build system.

CMOS VLSI Logic Designs — GPDK90 - Custom CMOS standard cells and digital subsystems in 90-nm GPDK. Full transistor-level schematics, layout, pre/post-layout simulation, DRC, and LVS.

SAP-1 CPU in Logisim - Functional simulation of the Simple-As-Possible CPU with a hardwired Control Unit, system ROM, and custom bootloader for RAM initialization.

• A. U. Khalid, A. Tabassum, A. I. Rupom, M. F. Hossain and M. A. Hossain, "Design and Performance Comparison of 4-bit Ripple-Carry and Carry-Look-Ahead Adder in 90-nm CMOS VLSI Technology" - 2nd IEEE QPAIN, April 2026. · Read on IEEE Xplore

Chittagong University of Engineering and Technology (CUET) - B.Sc. ETE, VLSI Major · 2022–2026

• Final Year CGPA: 3.78/4.00 · A+ in all Advanced VLSI Design courses

Dhaka College - HSC, Science · GPA: 5.0/5.0, General Government Scholarship

Ideal School and College, Motijheel - SSC, Science · GPA: 5.0/5.0, Talent Pool Government Scholarship

• CUET Chess Club - President · July 2025–Present · Organized tournaments and hosted regular sessions.
• AshesToFlame Records - Founder / Co-Owner · 2019–2023 · Music production, release workflow, branding, and artist management.
• ETE Televerse 1.0 - Branding & Promotion Head · Nov 2025 · 200K+ social media impressions; produced the theme song "Eksathe".
• CUET Debating Society - Debater · 2022–2025 · Runners-up, Inter Department Debate Competition 2022.

• HDLs & Design: Verilog, SystemVerilog, SVA, UVM
• Architecture: RISC-V, Pipelined CPUs, AMBA (AXI4, APB), UART/SPI/I2C, DDR3, Custom Accelerators (IPU/TinyML)
• EDA & Physical Design: Vivado, OpenROAD Flow (RTL-to-GDSII), Yosys, OpenSTA, KLayout, Magic VLSI, Cadence Virtuoso
• Simulation & Verification: XSim, GTKWave, Verilator, UVM, SVA, Functional Coverage, Constrained-Random
• PDKs: SkyWater 130-nm (Sky130), Cadence GPDK 90-nm, ASAP7 7-nm FinFET
• Platforms: AMD Xilinx Basys 3 Artix-7 FPGA, Tang Nano 9K, ESP32
• Scripting & Automation: Python, C/C++, Bash, GNU Make, Git, Linux