First active edge at least one clock period from start

[christiaanb]

Fixes #2001

• Write a changelog entry (see changelog/README.md)
• Check copyright notices are up to date in edited files

[christiaanb]

For reviewers: with the change to the DDR test the Clash simulation and the HDL simulation now actually correspond. Before this change, it used to be that in the Clash simulation, outputverifier would trigger an assertion; where this assertion wasn't triggered in HDL simulation. Now neither the Clash simulation nor the HDL simulation trigger an assertion.

[alex-mckenna]

@christiaanb I unchecked the copyright notice TODO, I can see non-updated notices in at least clash-lib

[christiaanb]

All the files that have a copyright notice were originally published in 2021, and the copyright header mentions 2021; so it's all good. I rechecked the copyright notice TODO

[leonschoorl]

Why was there a difference in the resetGen prims behaviour between synchronous and asynchrous domains?
And why is that not longer needed?

[leonschoorl]

Suggested change

	makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> SystemVerilogState)
	makeSystemVerilog = makeHDL' (Clash.Backend.initBackend @SystemVerilogState)

[leonschoorl]

Suggested change

	genVerilog = doHDL (initBackend WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True) :: DomainMap -> VerilogState)
	genVerilog = doHDL (initBackend @VerilogState WORD_SIZE_IN_BITS HDLSYN True PreserveCase Nothing (AggressiveXOptBB False) (RenderEnums True))

[leonschoorl]

Suggested change

	makeSystemVerilog = makeHDL' (Clash.Backend.initBackend :: Int -> HdlSyn -> Bool -> PreserveCase -> Maybe (Maybe Int) -> AggressiveXOptBB -> RenderEnums -> DomainMap -> SystemVerilogState)
	makeSystemVerilog = makeHDL' (Clash.Backend.initBackend @SystemVerilogState)

[christiaanb]

The difference has always bogus, we used to have:

, { "BlackBox" :
    { "name"      : "Clash.Signal.Internal.asyncResetGen"
    , "kind" : "Declaration"
    , "type" :
"asyncResetGen :: Reset domain 'Asynchronous"
    , "template" :
"-- pragma translate_off
~RESULT <= '1',
           '0' after 2000 ps;
-- pragma translate_on"
    }
  }
, { "BlackBox" :
    { "name"      : "Clash.Signal.Internal.syncResetGen"
    , "kind" : "Declaration"
    , "type" :
"syncResetGen :: ( domain ~ 'Dom n clkPeriod
                 , KnownNat clkPeriod )
              => Reset domain 'Synchronous"
    , "template" :
"-- pragma translate_off
~RESULT <= '1',
           '0' after (2999 ps + ~LIT[1]0 ps);
-- pragma translate_on"
    }
  }

then in #428 we changed to:

, { "BlackBox" :
    { "name"      : "Clash.Signal.Internal.asyncResetGen"
    , "workInfo"  : "Always"
    , "kind" : "Declaration"
    , "type" :
"asyncResetGen :: Reset domain 'Asynchronous"
    , "template" :
"-- asyncResetGen begin
-- pragma translate_off
~RESULT <= '1',
           '0' after 3001 ps;
-- pragma translate_on
-- asyncResetGen end"
    }
  }
, { "BlackBox" :
    { "name"      : "Clash.Signal.Internal.syncResetGen"
    , "workInfo"  : "Always"
    , "kind" : "Declaration"
    , "type" :
"syncResetGen :: ( domain ~ 'Dom n clkPeriod
                 , KnownNat clkPeriod )
              => Reset domain 'Synchronous"
    , "template" :
"-- syncResetGen begin
-- pragma translate_off
~RESULT <= '1',
           '0' after (2999 ps + ~LIT[1] ps);
-- pragma translate_on
-- syncResetGen end"
    }
  }

so that the de-assertion always happened after 3000ps (which is the time all the clocks start (before this PR)).

Then in #527 those definitions got merged:

, { "BlackBox" :
    { "name"      : "Clash.Signal.Internal.resetGen"
    , "workInfo"  : "Always"
    , "kind" : "Declaration"
    , "type" :
"resetGen :: KnownDomain dom      => Reset dom"
    , "template" :
"-- resetGen begin
-- pragma translate_off
~RESULT <= ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI,
           ~IF ~ISACTIVEHIGH[0] ~THEN '0' ~ELSE '1' ~FI after ~IF~ISSYNC[0]~THEN(2999 ps + ~PERIOD[0] ps)~ELSE3001 ps~FI;
-- pragma translate_on
-- resetGen end"
    }
  }

By which time we should've already dropped the difference. Because both 3001ps and 2999ps + PERIOD[0]ps deassert before the second active edge; i.e. we cannot observe their difference.

[leonschoorl]

LGTM