clash-lang · leonschoorl · Sep 25, 2023 · Sep 1, 2023 · Oct 11, 2023 · Sep 19, 2023
diff --git a/cabal.project b/cabal.project
@@ -16,7 +16,7 @@ write-ghc-environment-files: always
 -- index state, to go along with the cabal.project.freeze file. update the index
 -- state by running `cabal update` twice and looking at the index state it
 -- displays to you (as the second update will be a no-op)
-index-state: 2023-09-12T05:36:44Z
+index-state: 2023-10-18T12:11:41Z
 
 -- For some reason the `clash-testsuite` executable fails to run without
 -- this, as it cannot find the related library...
@@ -81,4 +81,3 @@ package recursion-schemes
 
 package regex-tdfa
     optimization: 2
-
diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs
@@ -29,7 +29,7 @@ import           Prelude
 bbTF :: TemplateFunction
 bbTF = TemplateFunction used valid bbTemplate
  where
-  used = [3..6]
+  used = [2..5]
   valid = const True
 
 bbTemplate
@@ -39,7 +39,6 @@ bbTemplate
 bbTemplate bbCtx
   | [  _HasCallStack
     , _HasBiSignalDefault
-    , _KnownDomain
     , (intrinsicName, String, _)
     , (packagePin, packagePinTy, _)
     , (dOut, Bit, _)

diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs
@@ -30,7 +30,6 @@ bidirectionalBuffer
   :: forall ds dom
    . ( HasCallStack
      , HasBiSignalDefault ds
-     , KnownDomain dom
      )
   => Enable dom
   -- ^ output enable
@@ -56,7 +55,6 @@ bbECP5
   :: forall ds dom
    . ( HasCallStack
      , HasBiSignalDefault ds
-     , KnownDomain dom
      )
   => String
   -> BiSignalIn ds dom 1

diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs
@@ -30,8 +30,6 @@ tdpbram ::
   forall nAddrs domA domB nBytes a .
   ( HasCallStack
   , KnownNat nAddrs
-  , KnownDomain domA
-  , KnownDomain domB
   , KnownNat nBytes
   , BitSize a ~ (8 * nBytes)
   , NFDataX a
@@ -61,7 +59,7 @@ tdpbram ::
   ( Signal domA a
   , Signal domB a
   )
-tdpbram clkA enA addrA byteEnaA datA clkB enB addrB byteEnaB datB =
+tdpbram clkA@ExtractClockDom enA addrA byteEnaA datA clkB@ExtractClockDom enB addrB byteEnaB datB =
   -- [Note: eta port names for tdpbram]
   --
   -- By naming all the arguments and setting the -fno-do-lambda-eta-expansion GHC

diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs
@@ -44,8 +44,6 @@ used =
     :< _risingEdgeConstraintA
     :< _risingEdgeConstraintB
     :< knownNatNAddrs
-    :< _knownDomainA
-    :< _knownDomainB
     :< _nfDataX
     :< _bitpack
     :< nBytes
@@ -64,8 +62,6 @@ tdpbramBBTF bbCtx
     , _risingEdgeConstraintA
     , _risingEdgeConstraintB
     , _knownNatNAddrs
-    , _knownDomainA
-    , _knownDomainB
     , _nfDataX
     , _bitpack
     , (fmap fromIntegral . DSL.tExprToInteger -> Just nBytes)
@@ -155,8 +151,6 @@ tdpbramTclBBTF bbCtx
     , _risingEdgeConstraintA
     , _risingEdgeConstraintB
     , DSL.tExprToInteger -> Just depth
-    , _knownDomainA
-    , _knownDomainB
     , _nfDataX
     , _bitpack
     , DSL.tExprToInteger -> Just width

diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs
@@ -186,8 +186,6 @@ tdpbram# ::
   , DomainActiveEdge domA ~ 'Rising
   , DomainActiveEdge domB ~ 'Rising
   , KnownNat nAddrs
-  , KnownDomain domA
-  , KnownDomain domB
   , NFDataX a
   , BitPack a
   , KnownNat nBytes

diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs
@@ -129,10 +129,7 @@ defConfig = DcConfig
 -- disabled, the relevant signals will return 'XException'.
 dcFifo ::
   forall depth a write read .
-  ( KnownDomain write
-  , KnownDomain read
-
-  , NFDataX a
+  ( NFDataX a
 
   , KnownNat depth
   -- Number of elements should be between [2**4, 2**17] ~ [16, 131072].
@@ -156,7 +153,7 @@ dcFifo ::
   -- | Read enable @rd_en@
   Signal read Bool ->
   FifoOut read write depth a
-dcFifo DcConfig{..} wClk wRst rClk rRst writeData rEnable =
+dcFifo DcConfig{..} wClk@ExtractClockDom wRst rClk@ExtractClockDom rRst writeData rEnable =
   case (resetKind @write, resetKind @read) of
     (SSynchronous, SSynchronous) ->
       let

diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs
@@ -27,9 +27,10 @@ import GHC.Stack (HasCallStack)
 import Clash.Backend (Backend)
 import Clash.Core.TermLiteral (termToDataError)
 import Clash.Netlist.BlackBox.Types (BlackBoxFunction, emptyBlackBoxMeta)
+import Clash.Netlist.BlackBox.Util (getDomainConf)
 import Clash.Netlist.Types (TemplateFunction(..), BlackBox(BBFunction), BlackBoxContext)
-import Clash.Netlist.Util (orNothing, stripVoid)
-import Clash.Signal.Internal (ResetKind(..))
+import Clash.Netlist.Util (orNothing)
+import Clash.Signal.Internal (ResetKind(..),vResetKind)
 import Clash.Promoted.Nat (snatToNum)
 
 import qualified Clash.Primitives.DSL as DSL
@@ -51,8 +52,7 @@ import Clash.Cores.Xilinx.Internal
 --   * 'dcFifoTF': instantiates IP generated in @dcFifoTclTF@
 dcFifoBBF :: HasCallStack => BlackBoxFunction
 dcFifoBBF _isD _primName args _resTys
-  |  [  _knownDomainWrite, _knownDomainRead
-     , _nfDataX, _knownNatDepth
+  |  [ _nfDataX, _knownNatDepth
      , _constraint1, _constraint2, _hasCallStack
      , either error id . termToDataError -> dcConfig
      , _wClk, _wRst, _rClk, _rRst, _wData
@@ -93,22 +93,20 @@ dcFifoBBF _ _ args _ = error ("dcFifoBBF, bad args: " <> show args)
 dcFifoTF :: HasCallStack => DcConfig n -> TemplateFunction
 dcFifoTF config =
   TemplateFunction
-    -- ( KnownDomain write        -- 0
-    -- , KnownDomain read         -- 1
-    -- , NFDataX a                -- 2
-    -- , KnownNat depth           -- 3
-    -- , 4 <= depth               -- 4
-    -- , depth <= 17              -- 5
-    -- , HasCallStack             -- 6
+    -- ( NFDataX a                -- 0
+    -- , KnownNat depth           -- 1
+    -- , 4 <= depth               -- 2
+    -- , depth <= 17              -- 3
+    -- , HasCallStack             -- 4
     -- ) =>
-    -- DcConfig (SNat depth) ->   -- 7 Note: argument passed to this function
-    -- Clock write ->             -- 8
-    -- Reset write ->             -- 9
-    -- Clock read ->              -- 10
-    -- Reset read ->              -- 11
-    -- Signal write (Maybe a) ->  -- 12
-    -- Signal read Bool ->        -- 13
-    [0, 1, 7, 8, 9, 10, 11, 12, 13]
+    -- DcConfig (SNat depth) ->   -- 5 Note: argument passed to this function
+    -- Clock write ->             -- 6
+    -- Reset write ->             -- 7
+    -- Clock read ->              -- 8
+    -- Reset read ->              -- 9
+    -- Signal write (Maybe a) ->  -- 10
+    -- Signal read Bool ->        -- 11
+    [5, 6, 7, 8, 9, 10, 11]
     (const True)
     (dcFifoBBTF config)
  where
@@ -119,8 +117,7 @@ dcFifoBBTF ::
   BlackBoxContext ->
   State s Doc
 dcFifoBBTF DcConfig{..} bbCtx
-  | [  knownDomainWrite, knownDomainRead
-    , _nfDataX, _knownNatDepth
+  | [ _nfDataX, _knownNatDepth
     , _constraint1, _constraint2, _hasCallStack
     , _dcConfig
     , wClk, wRst, rClk, rRst, wDataM
@@ -174,29 +171,23 @@ dcFifoBBTF DcConfig{..} bbCtx
     rdEmptyBool <- DSL.boolFromBit "rd_empty_bool" rdEmpty
     rEnableBit <- DSL.boolToBit "rd_enable" rEnable
 
+    wDomConf <- DSL.liftToBlockState $ getDomainConf (DSL.ety wClk)
     wRstHigh <-
-      let domty = DSL.ety knownDomainWrite
-      in case stripVoid domty of
-           N.KnownDomain _ _ _ Synchronous _ _ ->
-             DSL.unsafeToActiveHigh "wr_rst_high" domty wRst
-           N.KnownDomain _ _ _ Asynchronous _ _ ->
+      case vResetKind wDomConf of
+           Synchronous ->
+             DSL.unsafeToActiveHigh "wr_rst_high" wRst
+           Asynchronous ->
              error $
                show 'dcFifoTF <> ": dcFifo only supports synchronous resets"
-           _ ->
-             error $ show 'dcFifoTF <> ": Bug: Not a KnownDomain " <>
-                     "constraint, mismatch between function and its blackbox"
 
+    rDomConf <- DSL.liftToBlockState $ getDomainConf (DSL.ety rClk)
     rRstHigh <-
-      let domty = DSL.ety knownDomainRead
-      in case stripVoid domty of
-           N.KnownDomain _ _ _ Synchronous _ _ ->
-             DSL.unsafeToActiveHigh "rd_rst_high" domty rRst
-           N.KnownDomain _ _ _ Asynchronous _ _ ->
+      case vResetKind rDomConf of
+           Synchronous ->
+             DSL.unsafeToActiveHigh "rd_rst_high" rRst
+           Asynchronous ->
              error $
                show 'dcFifoTF <> ": dcFifo only supports synchronous resets"
-           _ ->
-             error $ show 'dcFifoTF <> ": Bug: Not a KnownDomain " <>
-                     "constraint, mismatch between function and its blackbox"
 
     (rdDataCountUnsigned, rdDataCountPort) <-
       if dcReadDataCount then do
@@ -274,22 +265,20 @@ dcFifoBBTF _ bbCtx = error ("dcFifoBBTF, bad bbCtx: " <> show bbCtx)
 dcFifoTclTF :: HasCallStack => DcConfig n -> TemplateFunction
 dcFifoTclTF conf =
   TemplateFunction
-    -- ( KnownDomain write        -- 0
-    -- , KnownDomain read         -- 1
-    -- , NFDataX a                -- 2
-    -- , KnownNat depth           -- 3
-    -- , 4 <= depth               -- 4
-    -- , depth <= 17              -- 5
-    -- , HasCallStack             -- 6
+    -- ( NFDataX a                -- 0
+    -- , KnownNat depth           -- 1
+    -- , 4 <= depth               -- 2
+    -- , depth <= 17              -- 3
+    -- , HasCallStack             -- 4
     -- ) =>
-    -- DcConfig (SNat depth) ->   -- 7 Note: argument passed to this function
-    -- Clock write ->             -- 8
-    -- Reset write ->             -- 9
-    -- Clock read ->              -- 10
-    -- Reset read ->              -- 11
-    -- Signal write (Maybe a) ->  -- 12
-    -- Signal read Bool ->        -- 13
-    [7, 12]
+    -- DcConfig (SNat depth) ->   -- 5 Note: argument passed to this function
+    -- Clock write ->             -- 6
+    -- Reset write ->             -- 7
+    -- Clock read ->              -- 8
+    -- Reset read ->              -- 9
+    -- Signal write (Maybe a) ->  -- 10
+    -- Signal read Bool ->        -- 11
+    [5, 10]
     (const True)
     (dcFifoTclBBTF conf)
 
@@ -300,7 +289,7 @@ dcFifoTclBBTF ::
   State s Doc
 dcFifoTclBBTF DcConfig{..} bbCtx
   | [dcFifoName] <- N.bbQsysIncName bbCtx
-  , [  _knownDomainWrite, _knownDomainRead, _nfDataX
+  , [  _nfDataX
     , _knownNatDepth, _constraint1, _constraint2, _hasCallStack
     , _dcConfig, _wClk, _wRst, _rClk, _rRst, wDataM, _rEnable
     ] <- map fst (DSL.tInputs bbCtx)

diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs
@@ -43,8 +43,7 @@ vhdlBinaryPrim
   -> Primitive
 vhdlBinaryPrim primName tclTFName funcName =
   let
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< config
       :< clk
@@ -110,8 +109,7 @@ veriBinaryPrim
   -> Primitive
 veriBinaryPrim primName tclTFName funcName =
   let
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< config
       :< clk
@@ -148,8 +146,7 @@ vhdlFromUPrim
   -> Primitive
 vhdlFromUPrim primName funcName =
   let tfName = 'fromUTclTF
-      _knownDomain
-        :< _knownNat
+      _knownNat
         :< _hasCallStack
         :< clk
         :< en
@@ -186,7 +183,7 @@ vhdlFromUPrim primName funcName =
           ~GENSYM[#{funcName}][#{compSym}] : ~INCLUDENAME[0]
             port map (
               aclk => ~ARG[#{clk}],
-        ~IF~ISACTIVEENABLE[#{en}]~THEN      aclken => ~SYM[#{clk}],
+        ~IF~ISACTIVEENABLE[#{en}]~THEN      aclken => ~SYM[#{clkEnStdSym}],
         ~ELSE~FI      s_axis_a_tvalid => '1',
               s_axis_a_tdata => ~SYM[#{inpSlvSym}],
               m_axis_result_tvalid => open,
@@ -208,8 +205,7 @@ veriFromUPrim
 veriFromUPrim primName funcName =
   let
     tfName = 'fromUTclTF
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< clk
       :< en
@@ -245,8 +241,7 @@ vhdlFromSPrim
 vhdlFromSPrim primName funcName =
   let
     tfName = 'fromSTclTF
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< clk
       :< en
@@ -283,7 +278,7 @@ vhdlFromSPrim primName funcName =
           ~GENSYM[#{funcName}][#{compSym}] : ~INCLUDENAME[0]
             port map (
               aclk => ~ARG[#{clk}],
-        ~IF~ISACTIVEENABLE[#{en}]~THEN      aclken => ~SYM[#{clk}],
+        ~IF~ISACTIVEENABLE[#{en}]~THEN      aclken => ~SYM[#{clkEnStdSym}],
         ~ELSE~FI      s_axis_a_tvalid => '1',
               s_axis_a_tdata => ~SYM[#{inpSlvSym}],
               m_axis_result_tvalid => open,
@@ -305,8 +300,7 @@ veriFromSPrim
 veriFromSPrim primName funcName =
   let
     tfName = 'fromSTclTF
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< clk
       :< en
@@ -344,8 +338,7 @@ vhdlComparePrim
   -> Primitive
 vhdlComparePrim primName tclTFName funcName =
   let
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< clock
       :< enable
@@ -410,8 +403,7 @@ veriComparePrim
   -> Primitive
 veriComparePrim primName tclTFName funcName =
   let
-    _knownDomain
-      :< _knownNat
+    _knownNat
       :< _hasCallStack
       :< clock
       :< enable