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SPI: Generalize to multi-lane MOSI/MISO #2635

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SPI: Generalize to multi-lane MOSI/MISO #2635

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Commits on Apr 30, 2024

  1. SPI: Represent inputs/outputs as records

    @bgamari
    bgamari committed Apr 30, 2024
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  2. SPI: Generalize to multi-lane MISO/MISO 

    It is fairly common for single SPI bus to consist of a set of parallel
MISO/MOSI lanes (c.f. QSPI FLASH). For instance:

 * many multi-channel ADCs allow each converter to clock out over its
   own MISO lane to reduce the clockrate needed to achieve the designed
   conversion rate.

 * similarly, QSPI FLASH relies upon four bidirectional outputs to
   increase data rate.

Here we extend Clash.Cores.SPI to facilitate this use-case by
introducing `spiMaster'` and `spiSlave'`, which allow arbitrary
MISO/MOSI lane widths.
    @bgamari
    bgamari committed Apr 30, 2024
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