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Added thumb mode support for threadX GNU ports on armv7a platforms.
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https://msazure.visualstudio.com/One/_workitems/edit/26105175/
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@yajunxiaMS
yajunxiaMS committed Dec 12, 2023
1 parent 776ea21 commit 7653725
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Showing 203 changed files with 5,094 additions and 4,515 deletions.
52 changes: 24 additions & 28 deletions ports/cortex_a12/ac6/src/tx_thread_context_restore.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,16 +23,16 @@
#include "tx_user.h"
#endif

.arm

#ifdef TX_ENABLE_FIQ_SUPPORT
SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode
IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
SVC_MODE = 0x93 // Disable IRQ, SVC mode
IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
.arm
#endif

SVC_MODE = 0x13 // SVC mode
IRQ_MODE = 0x12 // IRQ mode

.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
Expand All @@ -45,15 +45,14 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore
since it will never be called 16-bit mode. */

.arm
.text
.align 2
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore ARMv7-A */
/* 6.3.0 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
Expand Down Expand Up @@ -94,6 +93,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
/* #include tx_user.h, */
/* resulting in version 6.3.0 */
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
.global _tx_thread_context_restore
Expand Down Expand Up @@ -129,9 +131,9 @@ _tx_thread_context_restore:
/* Just recover the saved registers and return to the point of
interrupt. */

LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
MSR SPSR_cxsf, r0 // Put SPSR back
LDMIA sp!, {r0-r3} // Recover r0-r3
POP {r0-r3} // Recover r0-r3
MOVS pc, lr // Return to point of interrupt

__tx_thread_not_nested_restore:
Expand Down Expand Up @@ -160,26 +162,23 @@ __tx_thread_no_preempt_restore:
/* Pickup the saved stack pointer. */

/* Recover the saved context and return to the point of interrupt. */
LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
MSR SPSR_cxsf, r0 // Put SPSR back
LDMIA sp!, {r0-r3} // Recover r0-r3
POP {r0-r3} // Recover r0-r3
MOVS pc, lr // Return to point of interrupt

__tx_thread_preempt_restore:

LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers
POP {r3, r10, r12, lr} // Recover temporarily saved registers
MOV r1, lr // Save lr (point of interrupt)
MOV r2, #SVC_MODE // Build SVC mode CPSR
MSR CPSR_c, r2 // Enter SVC mode
CPS #SVC_MODE // Enter SVC mode
STR r1, [sp, #-4]! // Save point of interrupt
STMDB sp!, {r4-r12, lr} // Save upper half of registers
PUSH {r4-r12, lr} // Save upper half of registers
MOV r4, r3 // Save SPSR in r4
MOV r2, #IRQ_MODE // Build IRQ mode CPSR
MSR CPSR_c, r2 // Enter IRQ mode
LDMIA sp!, {r0-r3} // Recover r0-r3
MOV r5, #SVC_MODE // Build SVC mode CPSR
MSR CPSR_c, r5 // Enter SVC mode
STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack
CPS #IRQ_MODE // Enter IRQ mode
POP {r0-r3} // Recover r0-r3
CPS #SVC_MODE // Enter SVC mode
PUSH {r0-r3} // Save r0-r3 on thread's stack

LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR r0, [r1] // Pickup current thread pointer
Expand All @@ -192,13 +191,11 @@ __tx_thread_preempt_restore:
STR r2, [sp, #-4]! // Save FPSCR
VSTMDB sp!, {D16-D31} // Save D16-D31
VSTMDB sp!, {D0-D15} // Save D0-D15

_tx_skip_irq_vfp_save:

#endif

MOV r3, #1 // Build interrupt stack type
STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR
PUSH {r3, r4} // Save interrupt stack type and SPSR
STR sp, [r0, #8] // Save stack pointer in thread control
// block

Expand All @@ -223,6 +220,5 @@ __tx_thread_dont_save_ts:
__tx_thread_idle_system_restore:

/* Just return back to the scheduler! */
MOV r0, #SVC_MODE // Build SVC mode CPSR
MSR CPSR_c, r0 // Enter SVC mode
CPS #SVC_MODE // Enter SVC mode
B _tx_thread_schedule // Return to scheduler
29 changes: 19 additions & 10 deletions ports/cortex_a12/ac6/src/tx_thread_context_save.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,13 @@
#include "tx_user.h"
#endif

.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif

.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global __tx_irq_processing_return
Expand All @@ -31,15 +38,14 @@
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
since it will never be called 16-bit mode. */

.arm
.text
.align 2
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save ARMv7-A */
/* 6.3.0 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
Expand Down Expand Up @@ -79,6 +85,9 @@
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
/* #include tx_user.h, */
/* resulting in version 6.3.0 */
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
.global _tx_thread_context_save
Expand All @@ -90,7 +99,7 @@ _tx_thread_context_save:

/* Check for a nested interrupt condition. */

STMDB sp!, {r0-r3} // Save some working registers
PUSH {r0-r3} // Save some working registers
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSID if // Disable FIQ interrupts
#endif
Expand All @@ -101,15 +110,15 @@ _tx_thread_context_save:

/* Nested interrupt condition. */

ADD r2, r2, #1 // Increment the interrupt counter
ADD r2, #1 // Increment the interrupt counter
STR r2, [r3] // Store it back in the variable

/* Save the rest of the scratch registers on the stack and return to the
calling ISR. */

MRS r0, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r0, r10, r12, lr} // Store other registers
SUB lr, #4 // Adjust point of interrupt
PUSH {r0, r10, r12, lr} // Store other registers

/* Return to the ISR. */

Expand All @@ -129,7 +138,7 @@ _tx_thread_context_save:
__tx_thread_not_nested_save:

/* Otherwise, not nested, check to see if a thread was running. */
ADD r2, r2, #1 // Increment the interrupt counter
ADD r2, #1 // Increment the interrupt counter
STR r2, [r3] // Store it back in the variable
LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR r0, [r1] // Pickup current thread pointer
Expand All @@ -140,8 +149,8 @@ __tx_thread_not_nested_save:
/* Save minimal context of interrupted thread. */

MRS r2, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r2, r10, r12, lr} // Store other registers
SUB lr, #4 // Adjust point of interrupt
PUSH {r2, r10, r12, lr} // Store other registers

MOV r10, #0 // Clear stack limit

Expand Down Expand Up @@ -174,5 +183,5 @@ __tx_thread_idle_system_save:
POP {lr} // Recover ISR lr
#endif

ADD sp, sp, #16 // Recover saved registers
ADD sp, #16 // Recover saved registers
B __tx_irq_processing_return // Continue IRQ processing
24 changes: 14 additions & 10 deletions ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,13 @@
#include "tx_user.h"
#endif

.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif

#ifdef TX_ENABLE_FIQ_SUPPORT
DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts
#else
Expand All @@ -31,19 +38,14 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts
MODE_MASK = 0x1F // Mode mask
FIQ_MODE_BITS = 0x11 // FIQ mode bits


/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end
since it will never be called 16-bit mode. */

.arm
.text
.align 2
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_nesting_end ARMv7-A */
/* 6.3.0 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
Expand Down Expand Up @@ -88,8 +90,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
/* #include tx_user.h, */
/* resulting in version 6.3.0 */
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_nesting_end
.type _tx_thread_fiq_nesting_end,function
_tx_thread_fiq_nesting_end:
Expand All @@ -103,8 +111,4 @@ _tx_thread_fiq_nesting_end:
ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
MSR CPSR_c, r0 // Reenter IRQ mode

#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
24 changes: 14 additions & 10 deletions ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,23 +23,25 @@
#include "tx_user.h"
#endif

.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif

FIQ_DISABLE = 0x40 // FIQ disable bit
MODE_MASK = 0x1F // Mode mask
SYS_MODE_BITS = 0x1F // System mode bits


/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start
since it will never be called 16-bit mode. */

.arm
.text
.align 2
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_nesting_start ARMv7-A */
/* 6.3.0 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
Expand Down Expand Up @@ -81,8 +83,14 @@ SYS_MODE_BITS = 0x1F // System mode bits
/* 10-31-2023 Tiejun Zhou Modified comment(s), added */
/* #include tx_user.h, */
/* resulting in version 6.3.0 */
/* xx-xx-xxxx Yajun Xia Modified comment(s), */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_nesting_start
.type _tx_thread_fiq_nesting_start,function
_tx_thread_fiq_nesting_start:
Expand All @@ -95,8 +103,4 @@ _tx_thread_fiq_nesting_start:
// and push r1 just to keep 8-byte alignment
BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
MSR CPSR_c, r0 // Enter system mode
#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
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