Add VHDL syntax coloring

configs/vhdl.configuration.json

@@ -0,0 +1,11 @@
+{
+	"comments": {
+		"lineComment": "--",
+		"blockComment": []
+	},
+	"brackets": [
+		["{", "}"],
+		["[", "]"],
+		["(", ")"]
+	]
+}

package.json

@@ -157,6 +157,19 @@
                 }
             },
             {
+				"id": "vhdl",
+				"aliases": [
+					"VHDL",
+					"vhdl"
+				],
+				"extensions": [
+					".vhd",
+					".vhdl",
+					".vho"
+				],
+				"configuration": "./configs/vhdl.configuration.json"
+			},
+			{
                 "id": "sdc",
                 "aliases": [
                     "Synopsys Design Constraints"
@@ -251,6 +264,11 @@
                 "path": "./syntaxes/verilog-filelist.json"
             },
             {
+				"language": "vhdl",
+				"scopeName": "source.vhdl",
+				"path": "./syntaxes/vhdl.tmLanguage.json"
+			},
+			{
                 "language": "sdc",
                 "scopeName": "source.sdc",
                 "path": "./syntaxes/sdc.json"

syntaxes/systemverilog.tmLanguage.yaml

@@ -265,7 +265,7 @@ repository:
       - include: '#sv-rand'
   sv-control:
     match: >-
-      [ \t\r\n]*\b(initial|always|always_comb|always_ff|always_latch|final|assign|deassign|force|release|wait|forever|repeat|alias|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|clocking|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|matches|solve|before|expect|cross|ref|srandom|struct|chandle|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|wait_order|triggered|randsequence|context|pure|wildcard|new|forkjoin|unique|unique0|priority)\b
+      [ \t\r\n]*\b(initial|always|always_comb|always_ff|always_latch|final|let|assign|deassign|force|release|wait|forever|repeat|alias|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|clocking|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|matches|solve|before|expect|cross|ref|srandom|struct|chandle|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|wait_order|triggered|randsequence|context|pure|wildcard|new|forkjoin|unique|unique0|priority)\b
     captures:
       '1':
         name: keyword.control.systemverilog