Fixed autoinstantiation tripping on brackets and unpacked dimensions

[richzwart]

This should fix issue #168 where mdule instantiation cannot handle port arrays.

Additionally I found that the auto-instantiation will trip up on any expressions being included in port sizes or parameter defaults when they include the end brace ')'

module example #(parameter P_DATA_WIDTH = (8)) (
input wire clk,
input wire [P_DATA_WIDTH-1:0] data [1:0]
);
// something here
endmodule

Great work on this plugin!

[joecrop]

Thanks so much for your contribution @richzwart. Can you please add a test case or two here: https://github.com/eirikpre/VSCode-SystemVerilog/blob/master/src/test/ModuleInstantiator.test.ts ?