Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll

phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
enjoy-digital · Sep 26, 2024 · 90b1a18 · 90b1a18
2 parents 2b0156e + 3696ef8
commit 90b1a18
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/liteeth/phy/titaniumrgmii.py b/liteeth/phy/titaniumrgmii.py
@@ -131,7 +131,7 @@ def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256
         # -------
         self.specials += ClkInput(
             i = clock_pads.rx,
-            o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
+            o = self.cd_eth_rx.clk,
         )
 
         # TX Clk.
@@ -144,7 +144,7 @@ def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256
         # TX PLL.
         # -------
         self.pll = pll = TITANIUMPLL(platform)
-        pll.register_clkin(None,                  freq=125e6,           name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
+        pll.register_clkin(self.cd_eth_rx.clk,    freq=125e6)
         pll.create_clkout(self.cd_eth_rx,         freq=125e6, phase=0,  with_reset=False)
         pll.create_clkout(self.cd_eth_tx,         freq=125e6, phase=0,  with_reset=False)
         pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90)

diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py
@@ -131,7 +131,7 @@ def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256
         # -------
         self.specials += ClkInput(
             i = clock_pads.rx,
-            o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
+            o = self.cd_eth_rx.clk,
         )
 
         # TX Clk.
@@ -144,7 +144,7 @@ def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256
         # TX PLL.
         # -------
         self.pll = pll = TRIONPLL(platform)
-        pll.register_clkin(None,                  freq=125e6,           name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
+        pll.register_clkin(self.cd_eth_rx.clk,    freq=125e6)
         pll.create_clkout(self.cd_eth_rx,         freq=125e6, phase=0,  with_reset=False, is_feedback=True)
         pll.create_clkout(self.cd_eth_tx,         freq=125e6, phase=0,  with_reset=False)
         pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)