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core: riscv: Fix initial value of a0 in "detect_csr" ASM macro #552

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core: riscv: Fix initial value of a0 in "detect_csr" ASM macro

core: riscv: Fix initial value of a0 in "detect_csr" ASM macro #552

Triggered via push August 26, 2024 13:10
@gagachanggagachang
pushed 1789a57
dev-riscv-fix-detect-csr
Status Success
Total duration 57m 26s
Artifacts –

ci.yml

on: push
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make check (QEMUv8, BTI+MTE+PAC)
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