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core: riscv: Use sp as base register of load instructions #592

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core: riscv: Use sp as base register of load instructions

core: riscv: Use sp as base register of load instructions #592

Run time

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Job Run time
make check (QEMUv7)
43m 7s
make (multi-platform)
51m 11s
make check (QEMUv8)
1h 10m 21s
Code style
59s
make check (QEMUv8, BTI+MTE+PAC)
47m 44s
make check (QEMUv8, Hafnium)
51m 8s
make check (QEMUv8, Xen)
1h 1m 59s
make check (QEMUv8, Xen FF-A)
1h 4m 17s
6h 30m 46s