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core: riscv: use configuration options for RISC-V extensions
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RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, enable RVC and FPU extension for QEMU virt machine.

Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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lyctw authored and jforissier committed Aug 19, 2024
1 parent a3d76f1 commit 883402f
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Showing 2 changed files with 28 additions and 11 deletions.
7 changes: 4 additions & 3 deletions core/arch/riscv/plat-virt/conf.mk
Original file line number Diff line number Diff line change
@@ -1,5 +1,9 @@
$(call force,CFG_RV64_core,y)

# ISA extension flags
$(call force,CFG_RISCV_ISA_C,y)
$(call force,CFG_RISCV_FPU,y)

$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_TEE_CORE_DEBUG,n)
$(call force,CFG_CORE_RESERVED_SHM,n)
Expand All @@ -23,9 +27,6 @@ CFG_TEE_CORE_NB_CORE ?= 1
CFG_NUM_THREADS ?= 1
$(call force,CFG_BOOT_SYNC_CPU,y)

# RISC-V-specific flags
rv64-platform-isa ?= rv64imafdc_zicsr_zifencei

$(call force,CFG_RISCV_M_MODE,n)
$(call force,CFG_RISCV_S_MODE,y)
$(call force,CFG_RISCV_PLIC,y)
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32 changes: 24 additions & 8 deletions core/arch/riscv/riscv.mk
Original file line number Diff line number Diff line change
Expand Up @@ -88,19 +88,35 @@ core-platform-cppflags += -I$(arch-dir)/include
core-platform-subdirs += \
$(addprefix $(arch-dir)/, kernel mm tee) $(platform-dir)

# Default values for "-mcmodel", "-march", and "-abi" compiler flags.
# Platform-specific overrides are in core/arch/riscv/plat-*/conf.mk.
# Default values for "-mcmodel" compiler flag
riscv-platform-mcmodel ?= medany
rv64-platform-isa ?= rv64imafd
rv64-platform-abi ?= lp64d
rv32-platform-isa ?= rv32imafd
rv32-platform-abi ?= ilp32d

ifeq ($(CFG_RV64_core),y)
ISA_BASE = rv64ima
ABI_BASE = lp64
else
ISA_BASE = rv32ima
ABI_BASE = ilp32
endif
ifeq ($(CFG_RISCV_FPU),y)
ISA_D = fd
ABI_D = d
endif
ifeq ($(CFG_RISCV_ISA_C),y)
ISA_C = c
endif
ifeq ($(CFG_RISCV_ISA_ZBB),y)
ISA_ZBB = _zbb
endif

riscv-isa = $(ISA_BASE)$(ISA_D)$(ISA_C)$(ISA_ZBB)_zicsr_zifencei
riscv-abi = $(ABI_BASE)$(ABI_D)

rv64-platform-cflags += -mcmodel=$(riscv-platform-mcmodel)
rv64-platform-cflags += -march=$(rv64-platform-isa) -mabi=$(rv64-platform-abi)
rv64-platform-cflags += -march=$(riscv-isa) -mabi=$(riscv-abi)
rv64-platform-cflags += -Wno-missing-include-dirs
rv32-platform-cflags += -mcmodel=$(riscv-platform-mcmodel)
rv32-platform-cflags += -march=$(rv32-platform-isa) -mabi=$(rv32-platform-abi)
rv32-platform-cflags += -march=$(riscv-isa) -mabi=$(riscv-abi)

rv64-platform-cppflags += -DRV64=1 -D__LP64__=1
rv32-platform-cppflags += -DRV32=1 -D__ILP32__=1
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