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dts: st: add RCC support on stm32mp257f-ev1
Configure the clock tree for stm32mp257f-ev1 board. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) | ||
| /* | ||
| * Copyright (C) STMicroelectronics 2024 - All Rights Reserved | ||
| */ | ||
|
|
||
| &clk_hse { | ||
| clock-frequency = <40000000>; | ||
| }; | ||
|
|
||
| &clk_hsi { | ||
| clock-frequency = <64000000>; | ||
| }; | ||
|
|
||
| &clk_lse { | ||
| clock-frequency = <32768>; | ||
| }; | ||
|
|
||
| &clk_lsi { | ||
| clock-frequency = <32000>; | ||
| }; | ||
|
|
||
| &clk_msi { | ||
| clock-frequency = <16000000>; | ||
| }; | ||
|
|
||
| &rcc { | ||
| st,busclk = < | ||
| DIV_CFG(DIV_LSMCU, 1) | ||
| DIV_CFG(DIV_APB1, 0) | ||
| DIV_CFG(DIV_APB2, 0) | ||
| DIV_CFG(DIV_APB3, 0) | ||
| DIV_CFG(DIV_APB4, 0) | ||
| DIV_CFG(DIV_APBDBG, 0) | ||
| >; | ||
|
|
||
| st,flexgen = < | ||
| FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) | ||
| FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) | ||
| FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2) | ||
| FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) | ||
| FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) | ||
| FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1) | ||
| FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) | ||
| FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0) | ||
| FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16) | ||
| FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23) | ||
| FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 3) | ||
| FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0) | ||
| FLEXGEN_CFG(21, XBAR_SRC_HSI_KER, 0, 0) | ||
| FLEXGEN_CFG(22, XBAR_SRC_HSI_KER, 0, 0) | ||
| FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16) | ||
| FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16) | ||
| FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16) | ||
| FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3) | ||
| FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21) | ||
| FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1) | ||
| FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1) | ||
| FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19) | ||
| FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19) | ||
| FLEXGEN_CFG(33, XBAR_SRC_PLL4, 0, 23) | ||
| FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59) | ||
| FLEXGEN_CFG(35, XBAR_SRC_HSI_KER, 0, 3) | ||
| FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(39, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0) | ||
| FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11) | ||
| FLEXGEN_CFG(42, XBAR_SRC_PLL7, 0, 16) | ||
| FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23) | ||
| FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2) | ||
| FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(49, XBAR_SRC_PLL5, 0, 3) | ||
| FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3) | ||
| FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3) | ||
| FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5) | ||
| FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1) | ||
| FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) | ||
| FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1) | ||
| FLEXGEN_CFG(60, XBAR_SRC_PLL4, 0, 23) | ||
| FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7) | ||
| FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7) | ||
| FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) | ||
| >; | ||
|
|
||
| st,kerclk = < | ||
| MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46) | ||
| MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) | ||
| MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) | ||
| MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE) | ||
| MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28) | ||
| MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY) | ||
| MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32) | ||
| MUX_CFG(MUX_DTS, MUX_DTS_HSE) | ||
| MUX_CFG(MUX_RTC, MUX_RTC_LSE) | ||
| MUX_CFG(MUX_D3PER, MUX_D3PER_LSE) | ||
| MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF) | ||
| MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF) | ||
| >; | ||
|
|
||
| pll1: st,pll-1 { | ||
| st,pll = <&pll1_cfg_1200Mhz>; | ||
|
|
||
| pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { | ||
| cfg = <30 1 1 1>; | ||
| src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | ||
| }; | ||
|
|
||
| pll1_cfg_1500Mhz: pll1-cfg-1500Mhz { | ||
| cfg = <75 2 1 1>; | ||
| src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll2: st,pll-2 { | ||
| st,pll = <&pll2_cfg_600Mhz>; | ||
|
|
||
| pll2_cfg_600Mhz: pll2-cfg-600Mhz { | ||
| cfg = <30 1 1 2>; | ||
| src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll3: st,pll-3 { | ||
| st,pll = <&pll3_cfg_800Mhz>; | ||
|
|
||
| pll3_cfg_800Mhz: pll3-cfg-800Mhz { | ||
| cfg = <20 1 1 1>; | ||
| src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | ||
| }; | ||
|
|
||
| pll3_cfg_900Mhz: pll3-cfg-900Mhz { | ||
| cfg = <45 2 1 1>; | ||
| src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll4: st,pll-4 { | ||
| st,pll = <&pll4_cfg_1200Mhz>; | ||
|
|
||
| pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { | ||
| cfg = <30 1 1 1>; | ||
| src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll5: st,pll-5 { | ||
| st,pll = <&pll5_cfg_532Mhz>; | ||
|
|
||
| pll5_cfg_532Mhz: pll5-cfg-532Mhz { | ||
| cfg = <133 5 1 2>; | ||
| src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll6: st,pll-6 { | ||
| st,pll = <&pll6_cfg_500Mhz>; | ||
|
|
||
| pll6_cfg_500Mhz: pll6-cfg-500Mhz { | ||
| cfg = <25 1 1 2>; | ||
| src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
|
|
||
| pll7: st,pll-7 { | ||
| st,pll = <&pll7_cfg_835_51172Mhz>; | ||
|
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||
| pll7_cfg_835_51172Mhz: pll7-cfg-835-51172Mhz { | ||
| cfg = <167 4 1 2>; | ||
| src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>; | ||
| frac = < 0x1A3337 >; | ||
| }; | ||
| }; | ||
|
|
||
| pll8: st,pll-8 { | ||
| st,pll = <&pll8_cfg_594Mhz>; | ||
|
|
||
| pll8_cfg_594Mhz: pll8-cfg-594Mhz { | ||
| cfg = <297 5 1 4>; | ||
| src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>; | ||
| }; | ||
| }; | ||
| }; |
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