core: riscv: Apply mask/unmask exeptions when operating page table

Add missing thread_{mask/unmask}_exceptions() when we operate the page
table. This is referenced from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.com>

core/arch/riscv/mm/core_mmu_arch.c

@@ -410,6 +410,7 @@ void asid_free(unsigned int asid)
 
 bool arch_va2pa_helper(void *va, paddr_t *pa)
 {
+	uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL);
 	vaddr_t vaddr = (vaddr_t)va;
 	struct mmu_pgt *pgt = NULL;
 	struct mmu_pte *pte = NULL;
@@ -426,17 +427,20 @@ bool arch_va2pa_helper(void *va, paddr_t *pa)
 		pte = core_mmu_table_get_entry(pgt, idx);
 
 		if (core_mmu_entry_is_invalid(pte)) {
+			thread_unmask_exceptions(exceptions);
 			return false;
 		} else if (core_mmu_entry_is_leaf(pte)) {
 			*pa = pte_to_pa(pte) |
 			      (vaddr & (BIT64(RISCV_PGSHIFT) - 1));
+			thread_unmask_exceptions(exceptions);
 			return true;
 		}
 
 		pgt = phys_to_virt(pte_to_pa(pte),
 				   MEM_AREA_TEE_RAM_RW_DATA, sizeof(*pgt));
 	}
 
+	thread_unmask_exceptions(exceptions);
 	return false;
 }
 
@@ -449,6 +453,7 @@ bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va,
 			 unsigned int max_level,
 			 struct core_mmu_table_info *tbl_info)
 {
+	uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL);
 	struct mmu_pgt *pgt = NULL;
 	struct mmu_pte *pte = NULL;
 	unsigned int level = CORE_MMU_BASE_TABLE_LEVEL;
@@ -483,6 +488,7 @@ bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va,
 		level--;
 	}
 out:
+	thread_unmask_exceptions(exceptions);
 	return ret;
 }