core: riscv: core_mmu_arch: fix PPN field extraction from PTE

The upper bits of page table entry may contain other fields introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT and N bits, thus PPN field should be masked out with PTE_PPN. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Tested-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
gagachang · Aug 14, 2024 · eadb6be · eadb6be
1 parent 8448708
commit eadb6be
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diff --git a/core/arch/riscv/include/encoding.h b/core/arch/riscv/include/encoding.h
@@ -291,6 +291,7 @@
 #define PTE_A     0x040 /* Accessed */
 #define PTE_D     0x080 /* Dirty */
 #define PTE_SOFT  0x300 /* Reserved for Software */
+#define PTE_PPN   0x003FFFFFFFFFFC00 /* PPN */
 #define PTE_RSVD  0x1FC0000000000000 /* Reserved for future standard use */
 #define PTE_PBMT  0x6000000000000000 /* Svpbmt: Page-based memory types */
 #define PTE_N     0x8000000000000000 /* Svnapot: NAPOT translation contiguity */

diff --git a/core/arch/riscv/mm/core_mmu_arch.c b/core/arch/riscv/mm/core_mmu_arch.c
@@ -135,7 +135,7 @@ static unsigned long core_mmu_ptp_create(unsigned long ppn)
 
 static unsigned long core_mmu_pte_ppn(struct mmu_pte *pte)
 {
-	return pte->entry >> PTE_PPN_SHIFT;
+	return (pte->entry & PTE_PPN) >> PTE_PPN_SHIFT;
 }
 
 static unsigned long pa_to_ppn(paddr_t pa)