core: arm: Rename main_secondary_init_intc() to boot_secondary_init_i…

…ntc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by renameing to
boot_secondary_init_intc(), since interrupt controllers are always
initialized in boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core/arch/arm/kernel/boot.c

@@ -100,7 +100,7 @@ __weak void primary_init_intc(void)
 }
 
 /* May be overridden in plat-$(PLATFORM)/main.c */
-__weak void main_secondary_init_intc(void)
+__weak void boot_secondary_init_intc(void)
 {
 }
 
@@ -1227,7 +1227,7 @@ static void init_secondary_helper(unsigned long nsec_entry)
 	secondary_init_cntfrq();
 	thread_init_per_cpu();
 	init_sec_mon(nsec_entry);
-	main_secondary_init_intc();
+	boot_secondary_init_intc();
 	init_vfp_sec();
 	init_vfp_nsec();
 

core/arch/arm/plat-aspeed/platform_ast2600.c

@@ -65,7 +65,7 @@ void primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-aspeed/platform_ast2700.c

@@ -23,7 +23,7 @@ void primary_init_intc(void)
 	gic_init(0, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-corstone1000/main.c

@@ -26,7 +26,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-imx/main.c

@@ -116,7 +116,7 @@ void primary_init_intc(void)
 }
 
 #if CFG_TEE_CORE_NB_CORE > 1
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-imx/pm/cpuidle-imx7d.c

@@ -218,7 +218,7 @@ int imx7d_lowpower_idle(uint32_t power_state __unused,
 		gic_inited = 1;
 		DMSG("=== Back from Suspended ===\n");
 	} else {
-		main_secondary_init_intc();
+		boot_secondary_init_intc();
 		gic_inited = 0;
 	}
 

core/arch/arm/plat-k3/main.c

@@ -37,7 +37,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-ls/main.c

@@ -215,7 +215,7 @@ void primary_init_intc(void)
 	gic_init(gic_base + gicc_offset, gic_base + gicd_offset);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-rcar/main.c

@@ -92,7 +92,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-rockchip/main.c

@@ -27,7 +27,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-rzn1/main.c

@@ -45,7 +45,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-stm/main.c

@@ -137,7 +137,7 @@ void primary_init_intc(void)
 	gic_init(GIC_CPU_BASE, GIC_DIST_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-stm32mp1/main.c

@@ -158,7 +158,7 @@ void primary_init_intc(void)
 	stm32mp_register_online_cpu();
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 

core/arch/arm/plat-sunxi/main.c

@@ -128,7 +128,7 @@ void primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-ti/main.c

@@ -39,7 +39,7 @@ void primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-vexpress/main.c

@@ -53,7 +53,7 @@ void primary_init_intc(void)
 }
 
 #if !defined(CFG_WITH_ARM_TRUSTED_FW)
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/arm/plat-zynq7k/main.c

@@ -146,7 +146,7 @@ void primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void main_secondary_init_intc(void)
+void boot_secondary_init_intc(void)
 {
 	gic_cpu_init();
 }

core/arch/riscv/kernel/boot.c

@@ -120,7 +120,7 @@ __weak void primary_init_intc(void)
 }
 
 /* May be overridden in plat-$(PLATFORM)/main.c */
-__weak void secondary_init_intc(void)
+__weak void boot_secondary_init_intc(void)
 {
 }
 
@@ -171,7 +171,7 @@ static void init_secondary_helper(unsigned long nsec_entry)
 
 	thread_init_per_cpu();
 	init_sec_mon(nsec_entry);
-	secondary_init_intc();
+	boot_secondary_init_intc();
 
 	IMSG("Secondary CPU %zu initialized", pos);
 }

core/include/kernel/boot.h

@@ -59,7 +59,7 @@ void boot_init_secondary(unsigned long nsec_entry);
 #endif
 
 void primary_init_intc(void);
-void main_secondary_init_intc(void);
+void boot_secondary_init_intc(void);
 
 void init_sec_mon(unsigned long nsec_entry);
 void init_tee_runtime(void);