core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to initialize those console drivers
(e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>

core/arch/arm/kernel/boot.c

@@ -106,6 +106,11 @@ __weak void boot_secondary_init_intc(void)
 {
 }
 
+/* May be overridden in plat-$(PLATFORM)/main.c */
+__weak void plat_console_init(void)
+{
+}
+
 /* May be overridden in plat-$(PLATFORM)/main.c */
 __weak unsigned long plat_get_aslr_seed(void)
 {

core/arch/arm/plat-amlogic/main.c

@@ -13,7 +13,7 @@ static struct amlogic_uart_data console_data;
 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
 			CORE_MMU_PGDIR_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	amlogic_uart_init(&console_data, CONSOLE_UART_BASE);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-aspeed/platform_ast2600.c

@@ -70,7 +70,7 @@ void boot_secondary_init_intc(void)
 	gic_init_per_cpu();
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-aspeed/platform_ast2700.c

@@ -29,7 +29,7 @@ void boot_secondary_init_intc(void)
 	gic_init_per_cpu();
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-bcm/main.c

@@ -62,7 +62,7 @@ void plat_trace_ext_puts(const char *str)
 		bcm_elog_putchar(*p);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-corstone1000/main.c

@@ -31,7 +31,7 @@ void boot_secondary_init_intc(void)
 	gic_init_per_cpu();
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 		   CONSOLE_BAUDRATE);

core/arch/arm/plat-d02/main.c

@@ -16,7 +16,7 @@ static struct hi16xx_uart_data console_data;
 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
 			HI16XX_UART_REG_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	hi16xx_uart_init(&console_data, CONSOLE_UART_BASE,
 			 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-d06/main.c

@@ -11,7 +11,7 @@ static struct lpc_uart_data console_data __nex_bss;
 
 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, LPC_BASE, LPC_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	lpc_uart_init(&console_data, LPC_BASE, CONSOLE_UART_CLK_IN_HZ,
 		      CONSOLE_BAUDRATE);

core/arch/arm/plat-hikey/main.c

@@ -41,7 +41,7 @@ register_ddr(DRAM1_BASE, DRAM1_SIZE_NSEC);
 register_ddr(DRAM2_BASE, DRAM2_SIZE_NSEC);
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 		   CONSOLE_BAUDRATE);

core/arch/arm/plat-hisilicon/main.c

@@ -24,7 +24,7 @@ register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE,
 		CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-imx/main.c

@@ -97,7 +97,7 @@ register_ddr(CFG_DRAM_BASE, CFG_DDR_SIZE);
 register_ddr(CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE);
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 #ifdef CONSOLE_UART_BASE
 	imx_uart_init(&console_data, CONSOLE_UART_BASE);

core/arch/arm/plat-k3/main.c

@@ -42,7 +42,7 @@ void boot_secondary_init_intc(void)
 	gic_init_per_cpu();
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-ls/main.c

@@ -112,7 +112,7 @@ void plat_primary_init_early(void)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 #ifdef CFG_PL011
 	/*

core/arch/arm/plat-marvell/main.c

@@ -85,7 +85,7 @@ void boot_primary_init_intc(void)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 #if defined(PLATFORM_FLAVOR_armada7k8k)
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,

core/arch/arm/plat-mediatek/main.c

@@ -33,7 +33,7 @@ void boot_primary_init_intc(void)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	if (CFG_TEE_CORE_LOG_LEVEL != 0) {
 		serial8250_uart_init(&console_data, CONSOLE_UART_BASE,

core/arch/arm/plat-nuvoton/main.c

@@ -60,7 +60,7 @@ void boot_primary_init_intc(void)
 	gic_init(GICC_BASE, GICD_BASE);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U32, 2);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-poplar/main.c

@@ -20,7 +20,7 @@ register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
 /* for dynamic shared memory */
 register_dynamic_shm(DRAM0_BASE_NSEC, DRAM0_SIZE_NSEC);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE,
 		CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-rcar/main.c

@@ -65,7 +65,7 @@ static struct scif_uart_data console_data __nex_bss;
 uint32_t rcar_prr_value __nex_bss;
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	scif_uart_init(&console_data, CONSOLE_UART_BASE);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-rockchip/main.c

@@ -32,7 +32,7 @@ void boot_secondary_init_intc(void)
 	gic_init_per_cpu();
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 #if defined(CFG_EARLY_CONSOLE)
 	/*

core/arch/arm/plat-rpi3/main.c

@@ -39,7 +39,7 @@ register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
 
 static struct serial8250_uart_data console_data;
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-rzg/main.c

@@ -28,7 +28,7 @@ register_dynamic_shm(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
 
 static struct scif_uart_data console_data __nex_bss;
 
-void console_init(void)
+void plat_console_init(void)
 {
 	scif_uart_init(&console_data, CONSOLE_UART_BASE);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-rzn1/main.c

@@ -34,7 +34,7 @@ register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
 register_ddr(DRAM_BASE, DRAM_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U32, 2);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-sam/main.c

@@ -499,7 +499,7 @@ static struct atmel_uart_data console_data;
 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
 			CORE_MMU_PGDIR_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	atmel_uart_init(&console_data, CONSOLE_UART_BASE);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-sprd/console.c

@@ -32,7 +32,7 @@
 
 static struct sprd_uart_data console_data;
 
-void console_init(void)
+void plat_console_init(void)
 {
 	sprd_uart_init(&console_data, CONSOLE_UART_BASE);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-stm/main.c

@@ -56,7 +56,7 @@ TEE_Result tee_entry_std(struct optee_msg_arg *arg, uint32_t num_params)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	stih_asc_init(&console_data, UART_CONSOLE_BASE);
 }

core/arch/arm/plat-stm32mp1/main.c

@@ -76,7 +76,7 @@ service_init(platform_banner);
  */
 static struct stm32_uart_pdata console_data;
 
-void console_init(void)
+void plat_console_init(void)
 {
 	/* Early console initialization before MMU setup */
 	struct uart {

core/arch/arm/plat-stm32mp2/main.c

@@ -58,7 +58,7 @@ service_init(platform_banner);
  */
 static struct stm32_uart_pdata console_data;
 
-void console_init(void)
+void plat_console_init(void)
 {
 #ifdef CFG_STM32_UART
 	/* Early console initialization before MMU setup */

core/arch/arm/plat-sunxi/main.c

@@ -88,7 +88,7 @@ static void tzpc_init(void);
 
 static struct serial8250_uart_data console_data;
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data,
 			     CONSOLE_UART_BASE,

core/arch/arm/plat-synquacer/main.c

@@ -28,7 +28,7 @@ register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
 register_phys_mem_pgdir(MEM_AREA_IO_SEC, THERMAL_SENSOR_BASE,
 			CORE_MMU_PGDIR_SIZE);
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 		   CONSOLE_BAUDRATE);

core/arch/arm/plat-ti/main.c

@@ -108,7 +108,7 @@ void init_sec_mon(unsigned long nsec_entry)
 	memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk));
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-totalcompute/main.c

@@ -32,7 +32,7 @@ void boot_primary_init_intc(void)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 		   CONSOLE_UART_BAUDRATE);

core/arch/arm/plat-uniphier/main.c

@@ -40,7 +40,7 @@ void boot_primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	/* Init UART */
 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,

core/arch/arm/plat-versal/main.c

@@ -51,7 +51,7 @@ void boot_primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE,
 		   CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/arm/plat-vexpress/main.c

@@ -80,7 +80,7 @@ void boot_primary_init_intc(void)
 }
 #endif
 
-void console_init(void)
+void plat_console_init(void)
 {
 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
 		   CONSOLE_BAUDRATE);

core/arch/arm/plat-zynq7k/main.c

@@ -89,7 +89,7 @@ void plat_primary_init_early(void)
 	io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0);
 	register_serial_console(&console_data.chip);

core/arch/arm/plat-zynqmp/main.c

@@ -80,7 +80,7 @@ void boot_primary_init_intc(void)
 	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	cdns_uart_init(&console_data, CONSOLE_UART_BASE,
 		       CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);

core/arch/riscv/kernel/boot.c

@@ -124,6 +124,11 @@ __weak void boot_secondary_init_intc(void)
 {
 }
 
+/* May be overridden in plat-$(PLATFORM)/main.c */
+__weak void plat_console_init(void)
+{
+}
+
 void boot_init_primary_early(void)
 {
 	unsigned long e = PADDR_INVALID;

core/arch/riscv/kernel/sbi_console.c

@@ -55,7 +55,7 @@ static void sbi_console_init(struct sbi_console_data *pd)
 	pd->chip.ops = &sbi_console_ops;
 }
 
-void console_init(void)
+void plat_console_init(void)
 {
 	sbi_console_init(&console_data);
 	register_serial_console(&console_data.chip);

core/arch/riscv/plat-spike/main.c

@@ -13,7 +13,7 @@
 #ifdef CFG_RISCV_M_MODE
 static struct htif_console_data console_data __nex_bss;
 
-void console_init(void)
+void plat_console_init(void)
 {
 #ifdef HTIF_BASE
 	htif_console_init(&console_data, HTIF_BASE);

core/arch/riscv/plat-virt/main.c

@@ -29,7 +29,7 @@ void boot_secondary_init_intc(void)
 }
 #endif /* CFG_RISCV_PLIC */
 
-void console_init(void)
+void plat_console_init(void)
 {
 	ns16550_init(&console_data, UART0_BASE, IO_WIDTH_U8, 0);
 	register_serial_console(&console_data.chip);

core/include/kernel/boot.h

@@ -66,6 +66,7 @@ void init_tee_runtime(void);
 /* weak routines eventually overridden by platform */
 void plat_cpu_reset_early(void);
 void plat_primary_init_early(void);
+void plat_console_init(void);
 unsigned long plat_get_aslr_seed(void);
 unsigned long plat_get_freq(void);
 #if defined(_CFG_CORE_STACK_PROTECTOR) || defined(CFG_WITH_STACK_CANARIES)