Added yaml for some F425 peripherals

devices/gd32f425.yaml

@@ -8,3 +8,14 @@ _modify:
   name: "GD32F425"
 _include:
   - common_patches/gd32f425.yaml
+  - ../peripherals/pmu/pmu_f4.yaml
+  - ../peripherals/rcu/rcu_f4.yaml
+  - ../peripherals/ctc/ctc_f4.yaml
+  - ../peripherals/gpio/gpio_f4.yaml
+  - ../peripherals/exti/exti.yaml
+  - ../peripherals/crc/crc.yaml
+  - ../peripherals/trng/trng.yaml
+  - ../peripherals/dma/dma_f4.yaml
+  - ../peripherals/dbg/dbg_f4.yaml
+  - ../peripherals/iref/iref_f4.yaml
+  - ../peripherals/adc/adc_f4.yaml

peripherals/adc/adc_f4.yaml

@@ -0,0 +1,148 @@
+"ADC?":
+  STAT:
+    ROVF:
+      _read:
+        NoOverrun: [0, "No overrun occurred in routine data register"]
+        Overrun: [1, "Overrun overrun occurred in routine data register"]
+      _write:
+        Clear: [0, "Clear the routine data register overrun flag"]
+    STRC:
+      _read:
+        NotStarted: [0, "No regular channel conversion started"]
+        Started: [1, "Regular channel conversion has started"]
+      _write:
+        Clear: [0, "Clear the regular channel start flag"]
+    EOC:
+      _read:
+        NotComplete: [0, "Conversion is not complete"]
+        Complete: [1, "Conversion complete"]
+      _write:
+        Clear: [0, "Clear end of group conversion flag"]
+    WDE:
+      _read:
+        NoEvent: [0, "No analog watchdog event occurred"]
+        Event: [1, "Analog watchdog event occurred"]
+      _write:
+        Clear: [0, "Clear the analog watchdog event flag"]
+  CTL0:
+    ROVFIE:
+      Disabled: [0, "ROVF interrupt disabled"]
+      Enabled: [1, "ROVF interrupt enabled."]
+    DRES:
+      Bits12: [0, "12-bit resolution"]
+      Bits10: [1, "10-bit resolution"]
+      Bits8: [2, "8-bit resolution"]
+      Bits6: [3, "6-bit resolution"]
+    RWDEN:
+      Disabled: [0, "Analog watchdog disabled"]
+      Enabled: [1, "Analog watchdog enabled"]
+    DISNUM: [0, 7]
+    DISRC:
+      Disabled: [0, "Discontinuous mode on regular channels disabled"]
+      Enabled: [1, "Discontinuous mode on regular channels enabled"]
+    WDSC:
+      All: [0, "Analog watchdog enabled on all channels"]
+      Single: [1, "Analog watchdog enabled on a single channel"]
+    SM:
+      Disabled: [0, "Scan mode disabled"]
+      Enabled: [1, "Scan mode enabled"]
+    WDEIE:
+      Disabled: [0, "WDE interrupt disabled"]
+      Enabled: [1, "WDE interrupt enabled"]
+    EOCIE:
+      Disabled: [0, "EOC interrupt disabled"]
+      Enabled: [1, "EOC interrupt enabled"]
+    # WDCHSEL:
+    #   Channel: [0, 18]
+  CTL1:
+    SWRCST:
+      NoEffect: [0, "No effect"]
+      Reset: [1, "Start the conversion of a regular channel"]
+    ETMRC:
+      Disable: [0, "Disable external trigger conversion of regular channels"]
+      RisingEdge: [1, "Enable external trigger conversion of regular channels on rising edge"]
+      FallingEdge: [2, "Enable external trigger conversion of regular channels on falling edge"]
+      BothEdges: [3, "Enable external trigger conversion of regular channels on both edges"]
+    ETSRC:
+      Timer0Ch0: [0, "Timer 0 channel 0 event"]
+      Timer0Ch1: [1, "Timer 0 channel 1 event"]
+      Timer0Ch2: [2, "Timer 0 channel 2 event"]
+      Timer1Ch1: [3, "Timer 1 channel 1 event"]
+      Timer1Ch2: [4, "Timer 1 channel 2 event"]
+      Timer1Ch3: [5, "Timer 1 channel 3 event"]
+      Timer1Trgo: [6, "Timer 1 TRGO event"]
+      Timer2Ch0: [7, "Timer 2 channel 0 event"]
+      Timer2Trgo: [8, "Timer 2 TRGO event"]
+      Timer3Ch3: [9, "Timer 3 channel 3 event"]
+      Timer4Ch0: [10, "Timer 4 channel 0 event"]
+      Timer4Ch1: [11, "Timer 4 channel 1 event"]
+      Timer4Ch2: [12, "Timer 4 channel 2 event"]
+      Timer7Ch0: [13, "Timer 7 channel 0 event"]
+      Timer7Trgo: [14, "Timer 7 TRGO event"]
+      Exti11: [15, "EXTI line 11 event"]
+    DAL:
+      Right: [0, "Right alignment"]
+      Left: [1, "Left alignment"]
+    EOCM:
+      EndOfSequence: [0, "EOC bit is set at the end of a sequence of conversions"]
+      EndOfEach: [1, "EOC bit is set at the end of each conversion"]
+    DDM:
+      Disabled: [0, "DMA mode disabled"]
+      Enabled: [1, "DMA mode enabled"]
+    DMA:
+      Disabled: [0, "DMA request disabled"]
+      Enabled: [1, "DMA request enabled"]
+    RSTCLB:
+      _write:
+        Reset: [1, "Initialize calibration register start."]
+      _read:
+        Done: [0, "Calibration register initialized."]
+        Busy: [1, "Calibration register initializing."]
+    CLB:
+      _write:
+        Start: [1, "Start calibration"]
+      _read:
+        Done: [0, "Calibration complete"]
+        Busy: [1, "Calibration in progress"]
+    CTN:
+      Disabled: [0, "Continuous conversion disabled"]
+      Enabled: [1, "Continuous conversion enabled"]
+    ADCON:
+      Disabled: [0, "ADC disabled"]
+      Enabled: [1, "ADC enabled"]
+  "SAMPT?":
+    "SPT*":
+      Cycles3: [0, "Channel sample time is 3 cycles"]
+      Cycles15: [1, "Channel sample time is 15 cycles"]
+      Cycles28: [2, "Channel sample time is 28 cycles"]
+      Cycles56: [3, "Channel sample time is 56 cycles"]
+      Cycles84: [4, "Channel sample time is 84 cycles"]
+      Cycles112: [5, "Channel sample time is 112 cycles"]
+      Cycles144: [6, "Channel sample time is 144 cycles"]
+      Cycles480: [7, "Channel sample time is 480 cycles"]
+  # WDHT:
+  #   WDHT: [0, 0xFFF]
+  # WDLT:
+  #   WDLT: [0, 0xFFF]
+  # RSQ0:
+  #   RL: [0, 7]
+  # "RSQ?":
+  #   "RSQ*": [0, 18]
+  OVSAMPCTL:
+    TOVS:
+      Consecutive: [0, "All oversampled conversaions for a channel are done consecutively"]
+      Separate: [1, "Oversampled conversions for a channel done wit a separate trigger."]
+    # OVSS:
+    #   Shift: [0, 0b1000]
+    OVSR:
+      Times2: [0b0000, "Oversampling ratio is 2"]
+      Times4: [0b0001, "Oversampling ratio is 4"]
+      Times8: [0b0010, "Oversampling ratio is 8"]
+      Times16: [0b0011, "Oversampling ratio is 16"]
+      Times32: [0b0100, "Oversampling ratio is 32"]
+      Times64: [0b0101, "Oversampling ratio is 64"]
+      Times128: [0b0110, "Oversampling ratio is 128"]
+      Times256: [0b0111, "Oversampling ratio is 256"]
+    OVSEN:
+      Disabled: [0, "Oversampling disabled"]
+      Enabled: [1, "Oversampling enabled"]

peripherals/ctc/ctc_f4.yaml

@@ -0,0 +1,78 @@
+CTC:
+  CTL0:
+    SWREFPUL:
+      "Generate": [1, "Generates a software reference source sync pulse."]
+    AUTOTRIM:
+      Disabled: [0, "Hardware automatic trim disabled"]
+      Enabled: [1, "Hardware automatic trim enabled"]
+    CNTEN:
+      Disabled: [0, "CTC trim counter disabled"]
+      Enabled: [1, "CTC trim counter enabled"]
+    EREFIE:
+      Disabled: [0, "EREFIF interrupt disabled"]
+      Enabled: [1, "EREFIF interrupt enabled"]
+    ERRIE:
+      Disabled: [0, "ERRIF interrupt disabled"]
+      Enabled: [1, "ERRIF interrupt enabled"]
+    CKWARNIE:
+      Disabled: [0, "CKWARNIF interrupt disabled"]
+      Enabled: [1, "CKWARNIF interrupt enabled"]
+    CKOKIE:
+      Disabled: [0, "CKOKIF interrupt disabled"]
+      Enabled: [1, "CKOKIF interrupt enabled"]
+  CTL1:
+    REFPOL:
+      RisingEdge: [0, "Rising edge selected"]
+      FallingEdge: [1, "Falling edge selected"]
+    REFSEL:
+      GPIO: [0, "GPIO (CTC_SYNC) selected"]
+      LXTAL: [1, "LXTAL clock selected"]
+      Reserved1: [2, "Reserved"]
+      Reserved2: [3, "Reserved"]
+    REFPSC:
+      DIV1: [0, "Reference signal not divided"]
+      DIV2: [1, "Reference signal divided by 2"]
+      DIV4: [2, "Reference signal divided by 4"]
+      DIV8: [3, "Reference signal divided by 8"]
+      DIV16: [4, "Reference signal divided by 16"]
+      DIV32: [5, "Reference signal divided by 32"]
+      DIV64: [6, "Reference signal divided by 64"]
+      DIV128: [7, "Reference signal divided by 128"]
+  STAT:
+    REFDIR:
+      Up: [0, "CTC trim counter up-counting"]
+      Down: [1, "CTC trim counter down-counting"]
+    TRIMERR:
+      NoError: [0, "No trim value error occurs"]
+      ErrorOccurred: [1, "Trim value error occurs"]
+    REFMISS:
+      NoMiss: [0, "No reference sync pulse miss occurs"]
+      MissOccurred: [1, "Reference sync pulse miss occurs"]
+    CKERR:
+      NoError: [0, "No clock trim error occurs"]
+      ErrorOccurred: [1, "Clock trim error occurs"]
+    EREFIF:
+      NoReference: [0, "No expected reference occurs"]
+      ReferenceOccurred: [1, "Expected reference occurs"]
+    ERRIF:
+      NoError: [0, "No error occurs"]
+      ErrorOccurred: [1, "An error occurs"]
+    CKWARNIF:
+      NoWarning: [0, "No clock trim warning occurs"]
+      WarningOccurred: [1, "Clock trim warning occurs"]
+    CKOKIF:
+      NotOK: [0, "No clock trim OK occurs"]
+      OK: [1, "Clock trim OK occurs"]
+  INTC:
+    EREFIC:
+      _write:
+        Clear: [1, "Clear the EREFIF bit in CTC_STAT register"]
+    ERRIC:
+      _write:
+        Clear: [1, "Clear ERRIF, TRIMERR, REFMISS, and CKERR bits in CTC_STAT register"]
+    CKWARNIC:
+      _write:
+        Clear: [1, "Clear CKWARNIF bit in CTC_STAT register"]
+    CKOKIC:
+      _write:
+        Clear: [1, "Clear CKOKIF bit in CTC_STAT register"]

peripherals/dbg/dbg_f4.yaml

@@ -0,0 +1,44 @@
+DBG:
+  ID:
+    ID_CODE: [0, 0xFFFFFFFF]
+  CTL0:
+    TRACE_IOEN:
+      Disabled: [0, "Trace pin allocation disabled"]
+      Enabled: [1, "Trace pin allocation enabled"]
+    STB_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled:
+        [
+          1,
+          "In standby mode the AHB clock and system clock are provided by IRC16M, a system reset generated when exiting standby mode.",
+        ]
+    DSLP_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled:
+        [
+          1,
+          "In deep-sleep mode the AHB clock and system clock are provided by IRC16M, a system reset generated when exiting deep-sleep mode.",
+        ]
+    SLP_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled: [1, "In sleep mode the AHB clock is on"]
+  CTL1:
+    "CAN*_HOLD":
+      Continue: [0, "Continue running the CAN as usual"]
+      Stop: [1, "Hold the CAN for debug when the core is halted"]
+    "I2C*_HOLD":
+      Continue: [0, "Continue running I2C as usual"]
+      Stop: [1, "Hold the I2C timeout for debug when the core is halted"]
+    "TIMER*_HOLD":
+      Continue: [0, "Continue running the timer as usual"]
+      Stop: [1, "Hold the timer counter for debug when the core is halted"]
+    FWDGT_HOLD:
+      Continue: [0, "Continue running the free watchdog timer as usual"]
+      Stop: [1, "Hold the free watchdog timer for debug when the core is halted"]
+    RTC_HOLD:
+      Continue: [0, "Continue running the RTC as usual"]
+      Stop: [1, "Hold the RTC for debug when the core is halted"]
+  CTL2:
+    "TIMER*_HOLD":
+      Continue: [0, "Continue running the timer as usual"]
+      Stop: [1, "Hold the timer counter for debug when the core is halted"]