Flatten input port values prior to using if SystemVerilog type annota…

…tions are used.

Indexing directly into structs can cause lint errors so create a bitvector copy of the input port value and use that instead.

PiperOrigin-RevId: 684501915

xls/codegen/module_builder.cc

@@ -422,9 +422,21 @@ LogicRef* ModuleBuilder::AddInputPort(std::string_view name, int64_t bit_count,
                                       std::optional<std::string_view> sv_type) {
   auto* raw_bits_type = file_->BitVectorType(bit_count, SourceInfo());
   if (sv_type && options_.emit_sv_types()) {
-    return module_->AddInput(
+    LogicRef* port = module_->AddInput(
         SanitizeIdentifier(name),
         file_->ExternType(raw_bits_type, *sv_type, SourceInfo()), SourceInfo());
+    if (!sv_type.has_value()) {
+      return port;
+    }
+    // If a SystemVerilog type is specified then create a flattened copy of the
+    // value for use inside the module because bit indexing into structs can
+    // cause lint warnings.
+    LogicRef* wire =
+        module_->AddWire(absl::StrCat(SanitizeIdentifier(name), "_flattened"),
+                         file_->BitVectorType(bit_count, SourceInfo()),
+                         SourceInfo(), input_section());
+    input_section()->Add<ContinuousAssignment>(SourceInfo(), wire, port);
+    return wire;
   }
   return module_->AddInput(SanitizeIdentifier(name), raw_bits_type,
                            SourceInfo());

xls/codegen/testdata/block_generator_test_InstantiatedBlockWithExternStructPorts.svtxt

@@ -62,23 +62,27 @@ module my_block(
   input  pkg::small_arr_t y,
   output  pkg::big_arr_t out
 );
+  wire [159:0] x_flattened;
+  assign x_flattened = x;
+  wire [159:0] y_flattened;
+  assign y_flattened = y;
   wire [31:0] instantiation_output_43[5];
   wire [31:0] instantiation_output_44[5];
   wire [31:0] instantiation_output_47[10];
   wire [31:0] tuple_index_38[5];
   wire [31:0] tuple_index_40[5];
   wire [31:0] array_concat_45[10];
 
-  assign tuple_index_38[0] = x[31:0];
-  assign tuple_index_38[1] = x[63:32];
-  assign tuple_index_38[2] = x[95:64];
-  assign tuple_index_38[3] = x[127:96];
-  assign tuple_index_38[4] = x[159:128];
-  assign tuple_index_40[0] = y[31:0];
-  assign tuple_index_40[1] = y[63:32];
-  assign tuple_index_40[2] = y[95:64];
-  assign tuple_index_40[3] = y[127:96];
-  assign tuple_index_40[4] = y[159:128];
+  assign tuple_index_38[0] = x_flattened[31:0];
+  assign tuple_index_38[1] = x_flattened[63:32];
+  assign tuple_index_38[2] = x_flattened[95:64];
+  assign tuple_index_38[3] = x_flattened[127:96];
+  assign tuple_index_38[4] = x_flattened[159:128];
+  assign tuple_index_40[0] = y_flattened[31:0];
+  assign tuple_index_40[1] = y_flattened[63:32];
+  assign tuple_index_40[2] = y_flattened[95:64];
+  assign tuple_index_40[3] = y_flattened[127:96];
+  assign tuple_index_40[4] = y_flattened[159:128];
   assign array_concat_45[0] = instantiation_output_43[0];
   assign array_concat_45[1] = instantiation_output_43[1];
   assign array_concat_45[2] = instantiation_output_43[2];