add trace tool to support libva trace process

Signed-off-by: Lindong Wu <lindong.wu@intel.com>

tracetool/Modules/RTLog.py

@@ -0,0 +1,48 @@
+import os
+from util import *
+
+
+class traceHandler:
+    compMap = ['Common', 'CP', 'VP', 'Decode', 'Encode']
+
+    def __init__(self, core):
+        self.sharedCtx = core.getContext()
+        self.fp = None
+
+        core.regHandler('Intel-Media', 'MediaRuntimeLog', self.rtLog)
+        core.regHandler('Intel-Media', 'MediaRuntimeError', self.rtLog)
+
+    def writeOutput(self, line):
+        if self.fp == None:
+            self.fp = open(self.sharedCtx['Output'] + '_rtlog.txt', 'w')
+        self.fp.write(line)
+
+    def stripField(self, evt):
+        data = evt['data']
+        out = []
+        comp = int(GetEnumVal(data['LogId'])) >> 24
+        out.append(self.compMap[comp])
+        id = GetEnumName(data['LogId'])[3:] # remove prefix MT_
+        out.append(id)
+        if 'LogLevel' in data:
+            out.append(GetEnumName(data['LogLevel']))
+        else:
+            out.append('Error')
+        cnt = len(data)//2
+        for i in range(1, cnt):
+            n = GetEnumName(data['Id'+str(i)])[3:] # remove prefix MT_
+            v = GetEnumName(data['Value'+str(i)])
+            out.append(n+': '+v)
+        return out
+
+    def rtLog(self, evt):
+        out = self.stripField(evt)
+        txt = '{:<10d} {:<6} {:<6} {:<6s} {:<30s} {:<8s}'.format(evt['ts'], evt['pid'], evt['tid'], out[0], out[1], out[2])
+        for i in out[3:]:
+            txt += '    ' + i
+        self.writeOutput(txt+'\n')
+        return -1
+
+    def __del__(self):
+        if self.fp:
+            self.fp.close()