Merge pull request #127 from edwarddavidbaker/sync-platforms

MTL, ADL, TGL: Release event updates
intel · Jan 10, 2024 · 1b61e93 · 1b61e93
2 parents 234bb99 + 282a695
commit 1b61e93
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Showing 11 changed files with 816 additions and 120 deletions.
diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.23",
-    "DatePublished": "10/10/2023",
-    "Version": "1.23",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
+    "DatePublished": "12/04/2023",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [
@@ -4691,8 +4691,34 @@
       "EventCode": "0xb3",
       "UMask": "0x01",
       "EventName": "FP_ARITH_DISPATCHED.PORT_0",
-      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
-      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0",
+      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xb3",
+      "UMask": "0x01",
+      "EventName": "FP_ARITH_DISPATCHED.V0",
+      "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -4717,8 +4743,34 @@
       "EventCode": "0xb3",
       "UMask": "0x02",
       "EventName": "FP_ARITH_DISPATCHED.PORT_1",
-      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
-      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1",
+      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xb3",
+      "UMask": "0x02",
+      "EventName": "FP_ARITH_DISPATCHED.V1",
+      "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -4743,8 +4795,34 @@
       "EventCode": "0xb3",
       "UMask": "0x04",
       "EventName": "FP_ARITH_DISPATCHED.PORT_5",
-      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
-      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5",
+      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xb3",
+      "UMask": "0x04",
+      "EventName": "FP_ARITH_DISPATCHED.V2",
+      "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
+      "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -4802,13 +4880,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",
@@ -4828,13 +4906,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",
@@ -4854,13 +4932,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",

diff --git a/ADL/events/alderlake_gracemont_core.json b/ADL/events/alderlake_gracemont_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.23",
-    "DatePublished": "10/10/2023",
-    "Version": "1.23",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
+    "DatePublished": "12/04/2023",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [
@@ -3439,6 +3439,58 @@
       "PDISTCounter": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xe4",
+      "UMask": "0x01",
+      "EventName": "MISC_RETIRED.LBR_INSERTS",
+      "BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]",
+      "PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY]",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "1",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "0"
+    },
+    {
+      "EventCode": "0xe4",
+      "UMask": "0x01",
+      "EventName": "LBR_INSERTS.ANY",
+      "BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
+      "PublicDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "1",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "1",
+      "PDISTCounter": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xe6",
       "UMask": "0x01",

diff --git a/ADL/events/alderlake_uncore.json b/ADL/events/alderlake_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.23",
-    "DatePublished": "10/10/2023",
-    "Version": "1.23",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
+    "DatePublished": "12/04/2023",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [

diff --git a/ADL/events/alderlake_uncore_experimental.json b/ADL/events/alderlake_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.23",
-    "DatePublished": "10/10/2023",
-    "Version": "1.23",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
+    "DatePublished": "12/04/2023",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [