WSM-EP-SP: Release v4 event files

This commit releases WSM-EP-SP v4 events and updates mapfile.csv
accordingly.

Co-authored-by: Colin Ian King <colin.i.king@gmail.com>

WSM-EP-SP/events/WestmereEP-SP_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2022 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) 5600 series Based on the Westmere-EP Microarchitecture - V3",
-    "DatePublished": "04/14/2022",
-    "Version": "3",
+    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) 5600 series Based on the Westmere-EP Microarchitecture - V4",
+    "DatePublished": "08/17/2023",
+    "Version": "4",
     "Legend": ""
   },
   "Events": [
@@ -963,8 +963,8 @@
       "EventCode": "0xF7",
       "UMask": "0x4",
       "EventName": "FP_ASSIST.INPUT",
-      "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-      "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
+      "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
+      "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)",
       "Counter": "0,1,2,3",
       "SampleAfterValue": "20000",
       "MSRIndex": "0",
@@ -1983,8 +1983,8 @@
       "EventCode": "0xF1",
       "UMask": "0x7",
       "EventName": "L2_LINES_IN.ANY",
-      "BriefDescription": "L2 lines alloacated",
-      "PublicDescription": "L2 lines alloacated",
+      "BriefDescription": "L2 lines allocated",
+      "PublicDescription": "L2 lines allocated",
       "Counter": "0,1,2,3",
       "SampleAfterValue": "100000",
       "MSRIndex": "0",

mapfile.csv

@@ -4,7 +4,7 @@ GenuineIntel-6-1E,V4,/NHM-EP/events/NehalemEP_core.json,core,,,
 GenuineIntel-6-1F,V4,/NHM-EP/events/NehalemEP_core.json,core,,,
 GenuineIntel-6-1A,V4,/NHM-EP/events/NehalemEP_core.json,core,,,
 GenuineIntel-6-2F,V3,/WSM-EX/events/WestmereEX_core.json,core,,,
-GenuineIntel-6-25,V3,/WSM-EP-SP/events/WestmereEP-SP_core.json,core,,,
+GenuineIntel-6-25,V4,/WSM-EP-SP/events/WestmereEP-SP_core.json,core,,,
 GenuineIntel-6-2C,V5,/WSM-EP-DP/events/WestmereEP-DP_core.json,core,,,
 GenuineIntel-6-37,V15,/SLM/events/Silvermont_core.json,core,,,
 GenuineIntel-6-37,V15,/SLM/events/Silvermont_matrix.json,offcore,,,